Sunday, June 26, 2011

Neat Boulder hikes for visitors

So various people I work with/know come to Boulder, may want to try a hike but have limited time. Bring water!!! These are some ideas I like:

Quick but extremely impressive:
"Back of Green Mountain" driving time 30min?, hiking time: up to 1 hr up, 20 min down, even hiking slowish: From Broadway or anywhere, go west on Baseline, right up Flagstaff Mountain (look out for bicyclists going up), right through the fee area (you don't have to pay if you just drive through), after a really long time (maybe 5 miles, very mountainous), you will pass a sign saying "Leaving City of Boulder Mountain Parks/Fee Area/something", and you will also pass the 5-mile marker. Here, you can park for free at the side of the road, either side (do not block private drives), and if you look carefully on the left (South?) side of the road, you will see a trailhead with a sign and a map. The trail will meander for a bit, and has a crossing, but the way is pretty obvious. The summit is fantastic and there is a monument at the top showing where all the regional 14ers are. It is colder than in town, as you might expect.

Quick and casual:
1) NCAR nature trail: Go to NCAR, park, walk back a bit near the entrance road until you see where to cross the NCAR drive, and go to the nature trail. Views are great, and if you want to go farther, you can actually hike through the nature trail to the southwest side, to a trail which connects west to the Mesa Trail, and you can go a long way from there.

2) Settler's Park ("Red Rocks"): Not "The" Red Rocks, but just a nice short hike in the foothills west of downtown Boulder. There is a smallish parking lot near the intersection of Pearl and Canyon streets, but if it is full, there is some street parking east of there along Pearl. Can be parked up at busy times.

3) Along Bear Mountain Road, you will see an open area on the west side with a trailhead. This accesses both Bear Canyon, which starts as a road but becomes a trail, and also the Mesa Trail, which goes along the front of the foothills. I love Bear Canyon, and again you can go as far up this as you want, if you are over enthusiastic you are likely to end up at the top of Green Mountain (my favorite) or Bear Mountain, but it is especially nice in spring/mid-summer, when there is still some snowmelt. If you go all the way up, it is colder at the top!!! (note that during June/July 2017, the bottom of this is  closed for repair, but it can still be accessed from NCAR)

Other interesting general suggestions:
Cannot go wrong going to Chataqua, my favorite there is Royal Arch (far-ish), the Mesa Trail (a lot longer if you like), and the meadow right above the entrance. Gregory Canyon is also nearby and is partly shaded in the summer (parking kinda tight). These and others are mentioned here:

And finally, I just have to tell you that I think these people are impressive, but crazy:

Connie L. O'Dell
Sr. Verification Specialist
CO Consulting - Boulder, CO -

Monday, June 6, 2011

DAC 2011: SystemC &c, Must-See List (Cheesy), courtesy of John Cooley

Don't let John fool you, it's a very useful list...

(Lots of other good stuff also) ...
Mentor Catapult C synthesizes C/C++/SystemC to production quality RTL.       Now does incremental synthesis for ECOs plus it lets SystemC users       synthesize TLM models to create TLM-based virtual prototypes.  Used by       Qualcomm, Hitachi, Ericsson, ST, TI, Telegent, Panasonic, Fuji Xerox,       Toshiba, Fujitsu, Sanyo.  (booth 1542)  Ask for Thomas Bollaert.        

Forte Cynthesizer does SystemC synthesis to Verilog RTL of control and       datapath designs.  Brett's showing a "bus-based system with complex       interfaces in pin and TLM w/ highly abstract coding styles, pipelined       memories, untimed and timed code, and full SystemC support.  Sony,       Realtek, Samsung, Toshiba, Ricoh, Fujitsu, Sanyo, Megachips use it.       (booth 3417)  Ask for Brett Cline.  Freebie: caricatures        

Cadence C-to-Silicon Compiler synthesizes SystemC TLM to Verilog RTL.       They're very proud it's in the whole proprietary CDNS flow.  Will demo       an ECO.  Used by Fujitsu, Renesas, TI, Freescale, Casio, Hitachi.       (booth 2237)  Ask for Mark Warren.  Freebie: t-shirt        

Calypto SLEC 6.0 is *the* C/C++/SystemC equivalency checker.  Now has       a new word-level solver for inductive setups,  SystemC 2.2 support,       automatic wrapper and setup generation, CDNS C2S clock-gating, resets.       (booth 2012)  Ask for Anmol Mathur.  Freebie: none        

Carbon SoC Designer Plus creates cycle-accurate SystemC models of your       chip.  "Swap from the 100s of MIPS performance to 100% accuracy at any       software breakpoint."  Samsung, ST, ST-Ericsson, LG, Huawei, Broadcom       use it.  (booth 1914)  Ask for Bill Neifert.  Freebie: none        

CoFluent Studio does ESL modeling.  New release v4.0 can do automatic       generation of SystemC code from graphics for TLM-2.0 LT/AT and SCML2       interoperability.  Has an Eclipse-based C++ debugger where changes in       user-reserved areas in generated code is propagated back into your       graphical model.  Nokia, RIM, ST, Canon, Seagate, Toyota uses it.       (booth 1815)  Ask for Laurent Isenegger.  Freebie: none        

Bluespec BDW is a GUI for the development, analysis and debug of       high-level models, transactors, stimulus generators using Bluespec       System Verilog (BSV).  Now does source debug with designs in Verilog       simulation/emulation or FPGA prototype.  "This is enabled by BSV's       100% architectural transparency, which is different from high-level       designs that are C-based."  Used by Fujitsu, IBM, Intel and Qualcomm.       (booth 3031)  Ask for George Harper.  Freebie: a book on Bluespec        

Mentor Vista does TLM modeling style architecture design and virtual       prototyping, links to MENT embedded and ESL-to-RTL SoC verification.       Used by Honeywell.  (booth 1542)  Ask for Jon McDonald.        

Target Compiler MP Designer automatically parallelizes C code across       customer-defined multi-core architectures.  (i.e. load balancing)       NXP used it to get 2.9x on a new 3-DSP architecture, compared to a       single DSP, with an instruction-cycle utilization of 97% on each.       (booth 2227)  Ask for Erik Duymelinck.  Freebie: post-it pads        

Cadence SDS/VSP does HW/SW co-design "from architectural-level SW       development through system validation to post-RTL prototyping."  Does       SystemC and UVM.  Used by firmware/software teams at ARM, Nvidia,       Western Digital.  (booth 2237)  Ask for Leo Drucker.        

ApS Brno Codasip uses an architectural description language called       "Codal" and building blocks called "ASIPs" that all synthesizes to       Verilog HDL with known area, power, timing.  They're new to DAC.       (booth 3218)  Ask for Karel Masarik.  Freebie: none        

Mentor Embedded Sourcery CodeBench provides a "complete C/C++ dvlpmnt       environment for embedded software design."  It won the Embeddy Award       at the recent ESC 2011.  (booth 1542)  Ask for Stephen Olsen.
Lots of other good stuff...