Wednesday, September 7, 2011

CA Design verification (North and South)

Please feel free to contact Eric about these roles in southern/northern California.  
I've got nobody to suggest for California with that much experience.  :-)

Connie L. O'Dell 
Sr. Verification Specialist 
CO Consulting - Boulder, CO -

---------- Forwarded message ----------
From: Eric Williams <>
Date: Wed, Sep 7, 2011 at 4:47 PM
Subject: Great Verification Roles
I am working on some Verification Engineering positions. If you are actively looking for such a role, please send me your updated MS Word resume and we can get started right away: We have an excellent referral program and would like to reward you for your efforts. I look forward to hearing from you!

 Job Description:
*  Will be expected to contribute significantly to verification infrastructure development
*  Development of System Verilog/C++/C based protocol/traffic generators/checkers, development of test plan based on functional requirements as well as applicable standards requirements.
*  Will be responsible for definition, development and execution of self-checking tests for complex digital ASICs.

Job Requirements:
*  Masters degree desired, Bachelor's degree in CS/EE is required.
*  8 - 10 years of relevant experience in ASIC verification field.
*  Should have worked on developing/implementing test plans at the chip-level for a multi-million gate complex ASICs.
*  Fluent in System Verilog/C++/C, Verilog, and scripting languages.
*  Must have intimate knowledge of System Verilog/VMM simulation methodologies.
*  Experience with code coverage, formal verification tools; familiarity with evolving verification methodologies.
*  Very good communication skills and ability and desire to work in a geographically diverse team environment (peers and mentoring junior engineers).

Thank you,

Eric Williams
Terran Systems
Tel 408-727-9000
Fax 408-716-8882
Cell 408-634-8804

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