Wednesday, October 26, 2011

Free UVM webinar, courtesy of Doulos

From: Doulos Training <>
Subject: Free EasierUVM webinar - register now!

Easier UVM webinar

For more UVM Training and Resources: Visit
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Easier UVM Webinar November 2011
On-line Training Event Invitation

Event: Easier UVM Webinar
Live on-line training
Duration: 2 hours (two 1 hour sessions)
Cost: FREE!
Schedule and Registration: See below


Easier UVM is a set of guidelines for learning and using UVM, the Universal Verification Methodology for SystemVerilog and is aimed at mainstream designers rather than power users specialising in verification.

Presented by Doulos CTO, John Aynsley, the training will consist of 2 one-hour sessions, run on successive days (see below for options) and will be interactive with Q&A participation from delegates.
Content Summary:

Session 1: Introducing Easier UVM Components Transactions Sequences Phases Ports TLM Factory overrides Q&A

Session 2: Generation Configuration Starting a test Ending a test Layered sequences Requests and responses Copying and comparing transactions Q&A
Schedule and Registration:

This webinar will be broadcast twice, at convenient times for international audiences. Please review the times listed below and register for the most appropriate option to your time zone.

For North America (also UK and Europe if late afternoon preferred):
  • Session 1: Monday November 7
    Time: 9am-10am (PST) 12pm-1pm (EST) 5pm-6pm (GMT - UK)
  • Session 2: Tuesday November 8
    Time: 9am-10am (PST) 12pm-1pm (EST) 5pm-6pm (GMT - UK)

For UK, Europe and Asia:

  • Session 1: Wednesday November 9
    Time: 9am-10am (GMT - UK) 10am-11am (CET) 2.30pm-3.30pm (IST)
  • Session 2: Thursday November 10
    Time: 9am-10am (GMT - UK) 10am-11am (CET) 2.30pm-3.30pm (IST)

For more information visit


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