In this Issue: DVClub Events DVClub Austin held jointly with MTVCon: Dec 7
DVClub News DVClub in the Blogosphere
Software-Inspired Technique Predicts IC Verification Closure
RAM-Resident Database Speeds Verification Coverage Collection
Get Involved: Industry Events Attend MTVCon in Austin Dec 5-7
DAC 2012 - Key Deadlines
Sponsor News/Events MTVCon Scholarship - Deadline Extended [ARM]
CDNLive! - Call for Papers [Cadence]
Austin - December 7 - Cool River Cafe - Register
The Cortex-A15 Verification Story
Learn the details of verifying the Cortex-A15 MPCore: this processor has an out-of-order superscalar pipeline with a tightly-coupled low-latency level-2 cache which can be up to 4MB in size. It can be configured in clusters with up to 4 cores, and supports MP cache coherency in hardware. Additional improvements in floating point and NEON™ media performance result in devices that deliver the next-generation user experience for consumers as well as high-performance computation for web infrastructure applications. This processor introduces new technology that enables efficient handling of complex software environments including full hardware virtualization, Large Physical Address Extensions (LPAE) addressing up to 1TB of memory as well as error correction capability for fault-tolerance and soft-fault recovery.
This presentation will describe the advanced verification methodologies which are employed in the verification of Cortex-A15, including:
- Constrained random SystemVerilog unit level testbenches
- Coverage driven methodology utilizing black box and white box functional coverage for each unit
- Assertion based design where assertions are added by both verification engineers as well as RTL designers
- Top level (full CPU cluster) verification with multiple diverse random instruction generators, focusing on comprehensive ISA coverage and extensive stress of MP cache coherency
- System level (multiple CPU clusters + interconnect, memory controllers, graphics accelerators, other peripherals) emulation of the platform to enable booting of operating systems and running stress testing applications and workloads
- FPGA platforms to provide additional cost effective throughput
Bill Greene, Austin CPU Validation Manager, ARM, is the engineering manager for the CPU Validation Team at ARM in Austin. He previously worked at Intel on Itanium processor validation and firmware development, and as RTL and verification manager at Marvell developing ARM-based SoCs for mobile applications. He holds BSEE/BSCE and MSEE degrees from Purdue University.
Micah McDaniel, Principal Design Engineer, ARM, was the verification lead for the Cortex-A15 processor. At ARM he was previously an RTL designer and verification engineer on Cortex-A8. He has also done RTL design at Chicory Systems, and circuit design at IBM. He holds an MSEE from the University of Texas, and BSEE/BSCE and BSPHYS from Louisiana State University.
Register Now!
Recent DVClub Event Updates
Hands-On Verification -
Doug Smith, Engineer/Instructor, Doulos
Austin, August 15th
New Reference Link posted in lieu of slides
Additional Bonus: FREE WEBINAR: Easier UVM Training
Using Bug Arrival Rates to Predict the Future
- Greg Smith, Sr. Verification Manager, Oracle
Silicon Valley, August 17th
Slides Posted High Performance Collection of Coverage Metrics Using a Relational Database Backend
- James Roberts, Sr. Verification Engineer, Oracle
Silicon Valley, August 17th
Slides Posted DVClub in the Blogosphere
- with special thanks to blogger Richard Goering
DVClub Talk: Software-Inspired Technique Predicts IC Verification Closure What's the hardest question for a verification manager to answer? Greg Smith, senior verification manager at Oracle, found that out soon after he moved from design into verification at Hewlett-Packard some years ago. The question is, "when will you be done?"
DVClub Talk #2: RAM-Resident Database Speeds Verification Coverage Collection Metric-driven verification provides a great deal of valuable coverage data, but where are you going to store it all? Merging coverage data from hundreds or thousands of parallel simulation runs can pose a huge bottleneck. One way to avoid that bottleneck is to write to a memory-resident relational database, according to James Roberts, a verification engineer at Oracle who works with Sparc processors.
DAC 2012 Deadlines
Have an emerging topic that's timely, enlightenting, and relevant to various segments of the Design and Automation community?
Call for Contributions MTVCon 2011
12th Annual Microprocessor Test and Verification International Workshop
Join Leading Researchers & Practitioners in the Verification & Test Community
Austin, Texas - Hyatt Regency - December 5-7 Join attendees from industry and academia, including strong representation from companies such as AMD, Apple, ARM, Cadence, Freescale, IBM, Intel, Mentor Graphics, Oracle and Synopsys, among others. This year's theme is
Common Challenges and Solutions.
- Network with peers and luminaries.
- Exchange innovative ideas.
- Tackle difficult challenges in various processor and SOC design environments.
Design Verification Alerts from DVClub Sponsors
ARM Offers Scholarship for MTVCon - Deadline Extended!
ARM is offering numerous educational scholarships to the 12th Annual International Workshop on Microprocessor Test and Verification (MTVCon), to be held December 5-7, 2011 in Austin, TX. Eligibility is limited to graduate students and graduates new to the verification field. Deadline now extended.
For more info, visit:
ARM 2011 MTVCon Scholarship Know a grad student or a new grad who would be perfect for this?
Forward to a Friend! Cadence CDNLive! Silicon Valley - Calls for Papers
Abstracts are due before 5pm PST, on Friday, November 11, 2011
March 13-14th, 2012 -
San Jose, CA 
No comments:
Post a Comment