Accellera Systems Initiative™ is proud to sponsor The Design & Verification Conference & Exhibition (DVCon™). We are pleased to announce an exciting program of events for the first ever Accellera Systems Initiative Day on Monday, February 27!
Accellera Systems Initiative Day focuses on providing in-depth knowledge for our emerging and established standards to our user community. We are hosting a forum for SystemC users and conducting four tutorials on standards with sessions running concurrently throughout the day. We'll also host an interactive town hall lunch and discuss "What will success for the Accellera Systems Initiative look like?"
Accellera Systems Initiative Day is brought to you by our global sponsors: ARM, Cadence, CircuitSutra, Forte, Mentor Graphics, and Synopsys.
8:30am - 12:00pm
North American SystemC Users Group
8:30am - 5:00pm
Tutorial: UVM: Ready, Set, Deploy!
12:00pm - 1:30pm
Sponsored Luncheon: Town Hall Lunch with Accellera Systems Initiative
1:30pm - 5:00pm
Tutorial: An Introduction to IEEE 1666-2011, the New SystemC Standard
1:30pm - 3:00pm
Tutorial: An Introduction to the Unified Coverage Interoperability Standard
3:30pm - 6:30pm
Tutorial: Verification and Automation Improvement Using IP-XACT
North American SystemC User Group (NASCUG) Meeting XVII
NASCUG provides a unique forum for sharing SystemC™ user experiences among industry, research and universities. NASCUG operates independently but works in collaboration with the Accellera Systems Initiative to provide open forums for promoting information exchange. Our goal is to make SystemC end-users more effective through shared knowledge, user interaction and collaboration.
NASCUG topics and user presentations:
Accellera Systems Initiative: A New Synergy for Standards
What does C++2011 mean to SystemC?
Synchronization between a SystemC based off-line restbus simulator and a Hardware-In-the-Loop FlexRay network
Extending Fixed Sub-Systems at the TLM Level — Experiences from the FPGA World
A Generic Language for Hardware & Software, Are We There Yet? An Explorative Case Study Examining the Usage of SystemC for Multicore Programming
This tutorial will begin with an introduction to UVM™, concepts of structured verification methodology, base classes, resource configuration management, error handling, and report generation. It will continue with the UVM register package, including how to create and manage stimulus and checking at the register level. The morning session will conclude with a review of all of the topics, showing how they fit together in a complex SOC verification environment.
Introduction of these fundamental concepts will be followed by several real-life user experiences including lessons learned in preparing transition to UVM, architecting reusable testbenches, debug techniques and use of TLM 2.0 in real verification environments.
Join us at lunch to celebrate the emergence of the Accellera Systems Initiative. This "town hall" meeting will have no presentations, but rather will feature you, the forward-looking front-end standards community, exchanging ideas on the future of the new organization. Accellera Systems Initiative Officers, Board Members and Technical Working Groups Chairs will join this lively, open meeting. The main topic for this discussion will be:
What will success for the Accellera Systems Initiative look like?
There are many facets to this question, such as:
New standards that should be pursued
Synergies that ought to be exploited between existing or emerging standards
Relationships with or expansion into adjacent technology areas, e.g., the Embedded SW world
Extension of User Groups activity across all of our standards
Come prepared to discuss these and other factors that will put the Accellera Systems Initiative on a path to success that will eclipse even the stellar achievements of its two predecessors, Accellera™ and OSCI™.
Free with registration to any of the DVCon tutorials or the NASCUG meeting.
Tutorial: An Introduction to IEEE 1666-2011, the New SystemC Standard SystemC
The latest version of the IEEE 1666 Standard SystemC Language Reference Manual, published early in 2012, represents the marriage of the SystemC and TLM-2.0 libraries into a single standard, together with some significant improvements to SystemC relevant to both modeling and synthesis. This tutorial will be your first chance to see the new features of SystemC and TLM-2.0 presented in full now the new standard has been published, including a behind-the-scenes insight into the motivation behind the changes. We will also present examples illustrating the new features in action using the latest version of the OSCI Proof-of-Concept SystemC simulator, which is compliant to the new IEEE standard.
In addition, this tutorial will provide an introduction to the forthcoming draft Configuration Standard which targets the configuration of SystemC models. Key classes in the standard, which include parameters, brokers and accessors, will be described, and the use of the Configuration Standard to perform common tasks such as creating, initializing, updating, monitoring, hiding and locking parameter values will be demonstrated.
Tutorial: An Introduction to the Unified Coverage Interoperability Standard (UCIS)
This tutorial provides an overview of UCIS™ and its API and how users plan to enhance their verification flows using it. It provides a survey of many of the coverage metrics commonly used and how they are modeled in UCIS. The information that users will be able to access through UCIS will allow them to write their own applications to analyze, grade, merge and report coverage from one or more databases from one or more tool vendors. XML-based interchange format of UCIS, which provides a path to exchange coverage databases without requiring a common code library between tools and vendors, will also be discussed.
Tutorial: Verification and Automation Improvement Using IP-XACT with reception and poster session
This tutorial focuses on providing an opportunity to learn more about IP-XACT™ and how this standard can be used to enhance your IP based design and verification flow. The tutorial is composed of 4 main sub-sections and concludes with poster presentations, where you can check out current offerings from EDA companies:
Improving Verification efficiency using IP-XACT
Use-Case: Verification and Automation Improvement Using IP-XACT