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| Free DAC Breakfasts: HW/SW Co-Development, 28nm/20nm Challenges Posted: 14 May 2012 06:00 AM PDT Don't go into the frenzied activity of the Design Automation Conference (DAC) without a good breakfast! Fortunately, you can get a good breakfast and learn a lot from two events sponsored by Cadence Tuesday, June 5 and Wednesday, June 6 at the 49th DAC in San Francisco.
Tuesday June 5 Addressing Hardware/Software Co-Development, System Integration, and Time to Market This breakfast will feature speakers from Cadence and LSI Corp. Speakers will present the following topics:
The breakfast session will conclude with a panel discussion in which Cadence technologists and guests will answer your questions about system-level development challenges. Wednesday June 6 The Path to Yielding at 2(x)nm and Beyond This breakfast will include speakers from Cadence, IBM and Samsung. A panel will look at process and design challenges at advanced nodes and discuss what it takes to ramp up to volume production. The panel will examine challenges from the foundry, EDA and customer perspectives. Interested? Learn more about Cadence DAC lunches and breakfasts here Register for lunches and breakfasts here Learn about all Cadence DAC activities, including the Denali Party, here See you in San Francisco! Richard Goering
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| Free DAC Lunches: Custom/Analog Variability, ARM Low Power Processors in Mixed-Signal Designs Posted: 14 May 2012 06:00 AM PDT There is such a thing as a free lunch - if you're at the 49th Design Automation Conference (DAC) in San Francisco June 3-7. Cadence is sponsoring two lunches at which you can learn about two important technology topics - custom/analog variability, and the use of ARM processors in low-power, mixed-signal designs.
Monday June 4 Speakers at this lunch include Francois Lemery, CAD Project Manager, STMicroelectronics; Vinod Kariat, Fellow, Cadence; and Thomas Volden, Architect, Cadence. Speakers will show why variability is introducing new challenges at advanced process nodes, including layout-dependent effects. Cadence experts will demonstrate a comprehensive flow that can reduce total design time, manage layout-dependent effects, and optimize circuit performance without over-designing. Tuesday June 5 Speakers at this luncheon include Rob Cosaro, MCU System and Architecture group, NXP; Keith Clarke, VP Embedded Processors, ARM; John Murphy, Alliance Group Director, Cadence; Mladen Nizic, Engineering Director, Cadence; and Jamie Davey, ARM Alliance Director, Cadence. Speakers will participate in a roundtable discussion showing how you can integrate ARM Cortex-M processors and other design IP into your mixed-signal design more efficiently. Attendees will learn about the advantages of the new Cortex-M0 processor, ARM Cortex-M based MCUs from NXP, and the Cadence low-power and mixed-signal design solution. Interested? Learn more about Cadence DAC lunches and breakfasts here Register for lunches and breakfasts here Learn about all Cadence DAC activities, including the Denali Party, here See you in San Francisco! Richard Goering
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