This Friday - Free on-line training - SystemVerilog/VHDL/SystemC

Webinar: Start date: Duration: Presenter: Summary:

VHDL vs SystemVerilog vs SystemC » October 5, 2012 x1 1 hour session (all time zones covered) John Aynsley, Doulos CTO This webinar will give you an insight into how each of these languages are being used and their relative strengths and weaknesses.

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November 2012

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Webinar: Start date: Duration: Presenter: Summary:

Synthesis-Friendly SystemVerilog » November 2, 2012 x1 1 hour session (all time zones covered) John Aynsley, Doulos CTO This webinar will explore the features of SystemVerilog that are useful for RTL synthesis, showing how the RTL SystemVerilog language constructs have been optimized for productivity and reliability.

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Future on-line training events

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Webinar: Start date: Duration: Presenter: Summary:

Advanced VHDL Verification: OSVVM » TBC x1 1 hour session (all time zones covered) Alan Fitch, Principal Member Technical Staff This webinar will introduce you to Open Source VHDL Verification Methodology (OSVVM): what it does, how to use it, and how it compares with UVM.

Doulos Webinars

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