Thursday, February 7, 2013

DVClub Newsletter: January 2013, hardware design verification interest group, multiple locations

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DVClub Newsletter
In this Issue:
      Upcoming Events
          Silicon Valley - Dean Drako, CEO & President, IC Manage - February 14, 2013
      Past Events
          Delhi - DV Experts in the Delhi/NCR Region
          Austin - Zihno Jusufovic, Processor Verification, AMD
      DVClub Sponsors
Upcoming Events

IP Reuse Impact on DVM Across the Enterprise

Dean Drako, CEO & President, IC Manage

February 14, 2013
11:30 AM - 2:30 PM (PST)

Dave and Busters
940 Great Mall Dr.
Milpitas, CA 95035

Designing hardware is becoming more like designing software in that it is increasingly a process of 'continuous design'. To achieve continuous design, businesses are maximizing the reuse of IP modules across designs and design derivatives.

As such, companies must address the increasingly complex dependency management associated with the reuse of their IP blocks and subsystems, which evolve dynamically and incrementally as the IP is distributed and reused. Dependency management is needed for communication between IP developers, consumers, verification teams and management through the entire space of IP derivatives across the enterprise.

What is the most efficient process for ensuring design verification information flow and real-time sharing and access to this information? What information must be captured, encapsulated with the IP and shared - such as bug rollouts and propagation of fixes? What internal processes are needed to support such an infrastructure?

Speaker Bio:
Dean founded IC Manage in 2003, a company that he has helped expand to become the IC/SoC design and IP management technology leader. Dean was also founder, President and CEO of Barracuda Networks from 2003 to 2012, where he built and expanded Barracuda from a spam and virus firewall provider to a broad line enterprise technology company with more than 150,000 customers. Dean currently serves on Barracuda's Board of Directors.

Dean was also the founder of Boldfish, a leading provider of enterprise messaging solutions that was acquired by Siebel Systems in 2003. Before Boldfish, Dean was founder, president and CEO of Design Acceleration Inc. (DAI), maker of superior design analysis and verification tools, which was acquired by Cadence Design Systems. Dean has served as an entrepreneur in residence for SoftBank Venture Capital as well as vice president of product engineering at the 3DO Company. Dean holds a B.S. in electrical engineering from the University of Michigan, Ann Arbor and M.S. in electrical engineering from the University of California, Berkeley. In 2007, Dean was named "Technology Entrepreneur of the Year for Northern California" by Ernst & Young.

Register for the Event


Past Events

Delhi- Building A DV Ecosystem in Delhi NCR

DV Experts in the Delhi/NCR Region

Agnisys and Cadence brought DV Experts in the Delhi NCR together on December 19, 2012 to discuss the latest DV updates from around the world. DVClub in Delhi had a small start two years ago, but has since gained traction in its events. Most members work in verification companies including ST, Freescale, and HCL, to name a few. Also in attendance were entrepreneurs, students, managers, and even design engineers. This third DVClub event in Delhi gave members a chance to share ideas and solutions, creating an interactive environment.

Speakers: (and presentation links)
1.    Sandeep Jana, ST - TLM Based Software Control of UVCs
2.    Nitn Goel, Freescale - Accelerating Mixed Signal Verification Using System Verilog "Real"
3.    Ravi P Gupta, ST - Accelerated Code Coverage on HW Emulator
4.    Annu Gupta, ST - HDL Design Development Tracking Using Excel
5.    Mehul Kumar, Freescale - UVM Testbench Linter
6.    Chhavi Patni, ST - Verifying Performance of a (HDL) Design Block

Learn More About DVClub Delhi

Austin- Jaguar x86 Core Functional Verification

Zihno Jusufovic, Processor Verification, AMD

Jaguar is based on Bobcat first AMD low power core but there are significant design changes. The presentation contains a short summary of Jaguar architecture followed by a discussion of the unit and top level testbenches, the verification environment, and some of the challenges encounter during the functional verification of the core.

Speaker Bio:
Zihno Jusufovic is the technical lead on the Jaguar x86 core testbench. He has over 10 years of experience in verification of x86 processors, RISC processors and SOCs. Zihno earned his Master's Degree in Electrical Engineering from The University of Texas at Arlington.

Download the Presentation



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