Friday, February 22, 2013

SystemC learning (+UVM, System Verilog, ...) at DVCon
Event news: DVCon 2013 - San Jose, CA
Doulos at DVCon 2013:
 Visit the Doulos team at booth 501
 Tutorial: Migrating to UVM
 Tutorial: SystemC productivity
 Other learning opportunities
DVCon logo
Visit the Doulos DVCon booth for a special offer!

Grab an opportunity to catch up with the Doulos team at 
DVCon 2013
, which starts at the DoubleTree hotel, San Joseon February 25, and be among the first to find out about the forthcoming enhancements to the Doulos SystemVerilog training portfolio.

SystemVerilog Out Of The Box
All conference attendees will qualify for a special $200 discount voucher on Doulos SystemVerilog training, so make sure you register with your conference pass at the Doulos booth - 501! 

TUTORIAL: Lessons from the Trenches:
Migrating Legacy Verification Environments to UVM

All new technologies have end user challenges in terms of migration and/or adoption and UVM is no different. Migrating to the Universal Verification Methodology (UVM) from either OVM, VMM, Specman/’e’, or other verification BCL’s is not always easy. 

UVM logo

John AynsleyDoulos CTO John Aynsley will be speaking in this UVM migration and adoption session on Monday February 25th, in which you will hear the real stories from end users who work 'in the trenches' making this conversion magic happen for their teams as they move to UVM.

If you haven’t moved to UVM yet, this is a session you cannot miss.
Full UVM tutorial session details

SystemVerilog/UVM training and support UVM Resources Register for DVCon 2013
TUTORIAL: Increasing Productivity with SystemC in Complex System Design and Verification

After a decade of evolution, IEEE 1666™, aka SystemC™, is widely used for high level system design description and verification. As the system complexity increases, SystemC is becoming an enabler to build platforms for advanced design and verification techniques.

SystemC logo

UVM logoDoulos Senior Member, Technical Staff, David C Black, will be speaking at this tutorial on Monday February 25th, in which some experienced users and tool developers will share their interdisciplinary use of SystemC in building verification environments that provide early hardware access to software developers. 

More details about this System C session on Monday February 25

Other recommended learning opportunities at DVCon 2013

Wednesday February 27:
 The Finer Points of UVM: Tasting Tips for the Connoisseur
 A Tale of Two Languages: SystemVerilog and SystemC

For more information please call the Doulos team on 1 888 GO DOULOS or email
Copyright 2013 Doulos Limited. All rights reserved.

'via Blog this'

No comments:

Post a Comment