PCB/FPGA connectivity. free HDL edit, PCB Interconnect - HDL Works Design Tools

Interesting recommendation from a friend and former Bell Labs colleague, check it out:

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HDL Works offers various tools for the design and deployment of FPGAs in your hardware designs.

For starters, there is a handy FREE design tool, Scriptum!

Scriptum is a free text editor focused on VHDL and Verilog design, running on Windows and Linux. 

Using a multiple document window interface combined with tab pages it offers you an slick environment 

to edit VHDL, Verilog and other language files:

http://www.hdlworks.com/products/scriptum/index.html/

IO Checker 2.2:

You can verify hundreds of FPGA IO pins between PCB and FPGA in minutes!

When using large FPGA's on a PCB making sure that the FPGA pins are connected to the right 

signals on the PCB is a cumbersome task. IO Checker uses rules (based on regular expressions) to 

match the signal names in both the FPGA and PCB design environment. It allows the tool to validate 

groups of matches although individual signals can still differ. The rules can be generated automatically 

and be fine-tuned by the designer. The automated approach will often match 80% to 90% of all device pins. 

The main advantage over Mentor or Cadence tools is that IO Checker works in any flow and 
there only has to be a loose coupling between FPGA and PCB data. The rules generator in  combination with 

the sorted problem view allows engineers to validate a 1000+ pins device in half an hour.

Both BIG EDA competitors tools are intended to perform pin assignment  based on PCB placement.
If you just want to verify pin assignments to the PCB data (engineers often to do this in ISE/Quartus) 

IO Checker is much easier to use. Mentor has a good tool, but you must use it very regularly as it is also a difficult tool.
IO Checker is easy to learn and use!

Also,  IO Checker uses regular expressions to match differences between both FPGA and PCB that are intended.
(Quite often the FPGA/PCB names are a little different).

The flexibility of IO Checker allows it to be used in any design flow and does not require any design methodology. 

 

This link will give a detailed quick overview:
http://www.hdlworks.com/products/iochecker/index.html

Here is a demo movie:

http://www.hdlworks.com/products/iochecker/ioc_compare_viewlet_swf.html

You may also contact Craig Wolverton for a demo at: 

fcwolverton@comcast.net

or contact HDL Works directly at:

http://www.hdlworks.com

Another routing tool of interest is ConnTrace:

ConnTrace is a spin off from IO Checker. ConnTrace is used to verify interconnect 
    
between PCBs. It was developed for ASML (Europe) that designs racks with 
    
20+ boards via a backplane.
    

There are several great VHDL/Verilog design tools offered by HDL Works!
    

http://www.hdlworks.com/products/index.html
    

Again,  HDL Works direct page is 

    http://www.hdlworks.com