An interview with presenter Chris Komar on the DVCon 2013 paper 2.1, "Overcoming AXI Asynchronous Bridge Verification Challenges with AXI Assertion-Based Verification IP (ABVIP) and Formal Datapath Scoreboards"
Joseph Hupcey III speaks with Saurabh Shrivastava of Xilinx about his DVCon paper, "How to Kill 4 Birds with 1 Stone: In a Highly Configurable Design Using Formal to Validate Legal Configurations, Find Design Bugs, and Improve Testbench and Software Specifications" . (Authors: Saurabh Shrivastava, Kavita Dangi, Mukesh Sharma - Xilinx, Inc.; Darrow Chu - Cadence Design Systems, Inc.)
Joseph Hupcey III speaks with Amiq CEO Cristian Amitroaie discuss trends in supporting the unavoidable mix of design & verification languages in simple work flows, and innovations supporting specific languages like SystemVerilog, e, and VHDL.
Joe Hupcey III speaks with Nadav Chazan and Chris Dietrich of Cadence R&D about the DVCon tutorial "Fast Track Your UVM Debug Productivity with Simulation and Acceleration". Here Nadav and Chris outline some of the latest debug technologies and methodologies that increase the users' productivity and throughput -- in particular, how to combine the advantages of interactive and post-processing techniques.
In this interview Stuart Swan, senior architect at Cadence, discusses a methodology for using the same models for high-level synthesis and virtual prototyping. He spoke about this topic at a DVCon 2013 tutorial.