Friday, July 19, 2013

DVCon 2013 PlayList, verification et al, thanks to

Nice playlist for the design verification crowd:

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13 Videos. Showing from #1
DVCon 2013 - Meirav Nitzan of Xilinx on her poster "A Smart Generation of Design Attributes"
Meirav Nitzan of Xilinx R&D elaborates on her DVCon 2013 poster, "Taming the Beast: A Smart Generation of Design Attributes (Parameters) for Verification Closure Using Specman".
DVCon 2013 -- Neyaz Khan, Maxim, discusses mixed-signal (MS-SoC) verification
In this interview Neyaz Khan, distinguished member of technical staff at Maxim, discusses best practices for mixed-signal SoC verification -- the topic of a DVCon 2013 paper he co-authored.
DVCon 2013: AXI Asynchronous Bridge Verification with AXI ABVIP and Formal Datapath Scoreboards
An interview with presenter Chris Komar on the DVCon 2013 paper 2.1, "Overcoming AXI Asynchronous Bridge Verification Challenges with AXI Assertion-Based Verification IP (ABVIP) and Formal Datapath Scoreboards"
DVCon 2013: Saurabh Shrivastava of Xilinx on paper "How to Kill 4 Birds with 1 Stone Using Formal"
Joseph Hupcey III speaks with Saurabh Shrivastava of Xilinx about his DVCon paper, "How to Kill 4 Birds with 1 Stone: In a Highly Configurable Design Using Formal to Validate Legal Configurations, Find Design Bugs, and Improve Testbench and Software Specifications" . (Authors: Saurabh Shrivastava, Kavita Dangi, Mukesh Sharma - Xilinx, Inc.; Darrow Chu - Cadence Design Systems, Inc.)
DVCon 2013: Best Practices in Verification Planning
Co-author and presenter Paul Carzola shares some highlights of DVCon 2013 paper 4.2, "Best Practices in Verification Planning"
DVCon 2013 - Interview with AMIQ CEO Cristian Amitroaie
Joseph Hupcey III speaks with Amiq CEO Cristian Amitroaie discuss trends in supporting the unavoidable mix of design & verification languages in simple work flows, and innovations supporting specific languages like SystemVerilog, e, and VHDL.
DVCon 2013 - Tutorial: Fast Track Your UVM Debug Productivity with Simulation and Acceleration
Joe Hupcey III speaks with Nadav Chazan and Chris Dietrich of Cadence R&D about the DVCon tutorial "Fast Track Your UVM Debug Productivity with Simulation and Acceleration". Here Nadav and Chris outline some of the latest debug technologies and methodologies that increase the users' productivity and throughput -- in particular, how to combine the advantages of interactive and post-processing techniques.
DVCon 2013: Interview with Oski Technology CEO Vigyan Singhal
Joseph Hupcey III speaks with Vigyan Singhal, the CEO of from formal and ABV specialist Oski Technology, about how careful advanced planning can substantially reduce risk in verification projects.
DVCon 2013 -- Mike Stellfox of Cadence discusses verification planning
Mike Stellfox, Cadence fellow, discusses a DVCon panel he spoke at titled "Best Practices in Verification Planning."
DVCon 2013 -- John Biggs, IEEE 1801 chair, discusses new power format standard
In this interview John Biggs, principal engineer at ARM and chair of the IEEE 1801 (Unified Power Format) working group, discusses the new IEEE 1801-2013 standard and notes additions and improvements.
DVCon 2013 -- Ziv Binyamini of Cadence comments on "million design starts" panel
Ziv Binyamini, vice president and CTO of the System and Software Group at Cadence, comments on a panel he spoke at titled "Road to 1 Million Design Starts."
DVCon 2013 -- Stuart Swan of Cadence discusses high-level modeling
In this interview Stuart Swan, senior architect at Cadence, discusses a methodology for using the same models for high-level synthesis and virtual prototyping. He spoke about this topic at a DVCon 2013 tutorial.

DVCon 2013 PlayList

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