Thursday, December 5, 2013

12/6: Transform slow software into fast hardware on Zynq using Vivado HLS and SystemC

Cool-looking seminar from Doulos tomorrow; I hear that the presenter is very informative!

Transform Slow Software into Fast Hardware on a Zynq® All Programmable SoC using Vivado® HLS and SystemC/TLM-2.0

Format: Online training event
Duration: 1 hour 
Cost: FREE! 
Schedule and Registration: 
Friday December 6th, 2013 - Register below

SystemC Zynq

Webinar Overview:

In this webinar you will learn how to take a complex mathematical function that was found to run too slowly in software and transform it into a high performance hardware submodule within Zynq®. Before making the transformation, we will show you how to model the hardware submodule in SystemC/TLM-2.0 to provide assurance that once the hardware is implemented, performance will meet expectations.

This webinar will demonstrate the tool flow from concept to FPGA implementation by using Xilinx Vivado® HLS and Vivado IP Integrator. The source code of the examples will be made available to all who attend.
David BlackThe session will be presented by David C Black, Doulos Senior Member of Technical Staff and co-author of "SystemC: From the Ground Up", and will be broadcast on December 6th. It will consist of a one-hour session, (see below for details) and will be interactive with Q&A participation from delegates. 

Attendance is FREE!

What is SystemC? 
Developed by a group of companies forming the Open SystemC Initiative (OSCI), SystemC is a C++ class library typically used to model systems that have hardware and software content at the transaction level of abstraction. 

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Transform slow software into fast hardware on Zynq using Vivado HLS and SystemC

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