Friday, January 31, 2014

Jim Hogan's 15 chip/fab/EDA predictions for 2014, 2015, 2016 ..., thanks to Jim Hogan, Ed Lee, and John Cooley's ESNUG!

[Very interesting predictions, I do see many of the same trends]

( ESNUG 535 Item 11 ) ------------------------------------------- [01/30/14]

From: [ Ed Lee of Lee PR ]
Subject: Jim Hogan's 15 design/fab/EDA predictions for 2014, 2015, 2016...

Hi, John,

Last month, I had lunch with Jim Hogan at one of his companies in San Jose.
It being the end of 2013, I asked Jim what specific high tech predictions
he saw coming over the next few years.  He made 15 of them.  I underlined
each in my notes below.

    - Ed Lee
      Lee PR, Inc.                               Redwood City, CA

         ----    ----    ----    ----    ----    ----   ----

Mobile will be bigger.  Jim sees in 2014, the Internet-of-Things (IoT) will
spur a lot of new end-product development in wearable devices, medical
devices, smart devices -- that save energy or run faster on current energy.
This dovetails into an aging baby boom generation that will be managing
their own health into their eighties.

Jim notes that as we talk about Power/Performance/Area (PPA) these days for
chip development: 

    "Until now, we've been designing for maximum performance.  From
     here on, we'll need to design for maximum efficiency in terms
     of accommodating the SW apps that will run on these devices."

Starting in 2014, Jim sees the design trigger for the chip industry becoming
Functionality or Capability -- like on-body health sensors -- and then their
performance/power/cost will be done later.

The value of these devices, Jim says, will be driven by software:

    "The chip's design differentiation will be in the software.
     Hardware IP or blocks will become commodities.  The IoT is
     largely assembling known HW blocks with unique SW apps."

What's the upshot?  What should chip designers and EDA tool vendors work
toward?   Jim tells us that we'll see:

   - Increasingly complex designs, complexity in terms of function
     (i.e. hundreds of SW application processors per SoC).

   - Overall fewer design starts, but sub-90 nm starts will increase.
     We'll see fabs retooling -- like GlobalFoundries is doing in
     Singapore -- to get the older nodes into 300 mm wafer economics.

   - Each chip design will include 100's of IP blocks.

   - There will be 70%+ IP re-use and majority will be 3rd-party
     commercial IP.

   - More than 60% of chip design effort will be in software, making
     hardware verification impossible in some cases.

   - On-chip software will be much more complex.

   - Chips will have majority Dark Silicon with an always-on sentry.

   - A lot more sensors: we'll see more mixed-signal content IoT,
     as the IoT touches the real world.

What's EDA's opportunity?  To deal with astronomical increases in effort and
dollars spent for verification and software development.

    "Each major system company will make their own application-specific
     SoC.  In this way they can offer a differentiated product in the
     market.  The challenge for EDA is selling into a new systems market
     where application knowledge is king.  Automotive will be an early
     target.  It is, after all, the largest mobile appliance; look at
     CES this year -- it was all about cars."

Jim pointed to the verification effort:

    "Right now, verification consumes ~70% of design effort.  In many
     cases, there is no way to ensure a system's performance.  This is
     why we see emulation becoming ubiquitous and formal methods being
     adopted.  As designs get more complex, managers will have to keep
     buying more companies to get more engineers and IP."

What's the impact?

    "A lot of systems companies through 2008/2009 became very efficient
     and remain very cash rich.  They have been acquiring companies for
     IP and application knowledge.  This will continue and we will see
     the bigger SoC and system companies continue to acquire specialized
     and ongoing businesses."

    "There's still a design-by-verification attitude; there's way too
     much reliance on verification at RTL.  This won't scale!"

Jim concluded with:

    "Chip design teams will shortly need new design flow strategies.
     We'll see verification move above RTL, and a greater reliance
     on High Level C-to-RTL Synthesis (HLS)."

It's be interesting to see which of these 15 Jim Hogan predictions actually
come true over the next few years.

    - Ed Lee
      Lee PR, Inc.                               Redwood City, CA

From John Cooley's ESNUG at:

Jim Hogan's 15 chip/fab/EDA predictions for 2014, 2015, 2016 ...

'via Blog this'

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