|
| Another chance to view this webinar in which you will learn how to take a complex mathematical function that was found to run too slowly in software and transform it into a high performance hardware submodule within Zynq®. Before making the transformation, we will show you how to model the hardware submodule in SystemC/TLM-2.0 to provide assurance that once the hardware is implemented, performance will meet expectations. |
The webinar will demonstrate the tool flow from concept to FPGA implementation by using Xilinx Vivado® HLS and Vivado IP Integrator. The source code of the examples will be made available to all who attend.
The session will be presented by David C Black, Doulos Senior Member of Technical Staff and co-author of "SystemC: From the Ground Up", and will be broadcast on April 25th. It will consist of a one-hour session, (see below) and will be interactive with Q&A participation from delegates. Attendance is FREE!
Full description:
Transform Slow Software into Fast Hardware on a Zynq® All Programmable SoC
using Vivado® HLS and SystemC/TLM-2.0
Also check out the recent associated article written by David in Xilinx Xcell Journal Issue 87:
Make Slow Software Run Fast with Vivado HLS
 Schedule and Registration:
Friday April 25th: For UK, Europe and Asia
Time: 11am-12pm (GMT - UK)  12pm-1pm (CET) 3.30pm-4.30pm (IST)
Friday April 25th: For North America (also UK and Europe if late afternoon preferred)
Time: 9am-10am (PDT) 12pm-1pm (EDT) 5pm-6pm (BST - UK)
Want to find out more about Doulos first? Check out: www.doulos.com.
|
|
No comments:
Post a Comment