LAST CHANCE TO REGISTER The Keys to SystemC & TLM-2.0: How to be Successful
Format: Live online training Date: Friday October 31st, 2014 Duration: 1 hour (with live Q&A) Presenter: David C BlackCost: FREE! Schedule: All time zones covered
SystemC has become well-established as the language of choice for system modeling and virtual platform creation and integration, and is now being applied successfully for high level synthesis. SystemC models also frequently appear as reference models in the hardware verification flow.This session is aimed at hands-on hardware or software engineers who might know Verilog or C but have no previous experience of SystemC.
Schedule and Registration: Friday October 31st: For Europe and Asia Time: 11am-12pm (GMT - UK) 12pm-1pm (CET) 4.30pm-5.30pm (IST)
Friday October 31st: For North America (also Europe if late afternoon preferred) Time: 11am-12pm (PDT) 1pm-2pm (CDT) 2pm-3pm (EDT) 6pm-7pm (GMT - UK) Want to find out more about Doulos first? Check out: www.doulos.com.
This is an attempt to provide very basic and interesting information for new computer users from the senior community and very casual computer users, just to give you an idea what can be done most easily, and might be most valuable to you.
Once you have learned basic computer usage, interesting websites (to use these, put the pointer over the underlined blue text, then click the left mouse button):
A neat event to attend for anyone in the Verification field, esp. if you are in or around San Jose.
If you go, say hi to (Bob) K. for me! - Connie
"Oski Technology takes pride in helping our customers reach success through formal application and adoption. In 2013, Oski created the industry-wide Decoding Formal Club, with the goal to share formal knowledge and experience. Thus far the Club has been a lively forum for talks on formal sign-off methodology, achieving sign-off with bounded proof or abstraction models and building a formal test plan for sign-off.
The next Decoding Formal Club meeting will be held on Thursday, October 23, at the Computer History museum. Synopsys is sponsoring this event.
Vigyan Singhal will present another important topic related to formal sign-off ––End-to-End checkers. The presentation will explain what they are, and how to write them efficiently to achieve formal sign-off.
Syed Suhaib, CPU and Tegra formalverification team manager at NVIDIA, will share insights on his team’s real-world formal experience in verifying the recently announced NVIDIA Denver CPU.
Robert Kurshan, a noted formal verification pioneer, will talk about formal verification of cache coherence. He will cover its history and discuss actual requirements and practical options for verifying memory consistency using a model checker.
We hope you can join us for insightful talks, “formal” networking, museum tours, gifts and Indian food to celebrate Diwali. By joining us, you will be another step closer to success.
LAST CHANCE TO REGISTER Easier UVM - Making Verification Methodology More Productive
Format: Webinar Date: Friday October 17th, 2014 Duration: 1 hour (with live Q&A) Presenter: John Aynsley Cost: FREE! Schedule: All time zones covered
In this webinar we give a short introduction to UVM, the Universal Verification Methodology for SystemVerilog, by taking advantage of Easier UVM, a set of coding guidelines and a code generator that creates UVM code compliant to those guidelines. Easier UVM is an effective way of learning and adopting UVM, and furthermore the Easier UVM guidelines and code generator are freely available for use. Easier UVM was created to help individuals and project teams learn and then become productive with UVM as quickly as possible.