Thursday, October 16, 2014

Free Webinars: Easier/More Productive UVM, and SystemC/TLM-2.0, thanks to Doulos!

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Easier UVM - Making Verification Methodology
More Productive

Format: Webinar
Date: Friday October 17th, 2014
Duration: 1 hour (with live Q&A)
Presenter: John Aynsley
Cost: FREE!
Schedule: All time zones covered

Easier UVM Webinar Logo

In this webinar we give a short introduction to UVM, the Universal Verification Methodology for SystemVerilog, by taking advantage of Easier UVM, a set of coding guidelines and a code generator that creates UVM code compliant to those guidelines. Easier UVM is an effective way of learning and adopting UVM, and furthermore the Easier UVM guidelines and code generator are freely available for use. Easier UVM was created to help individuals and project teams learn and then become productive with UVM as quickly as possible.

Full description: Easier UVM - Making Verification Methodology more Productive

Schedule and Registration:

Friday October 17th: For Europe and Asia
Time: 10am-11am (BST - UK) 11am-12pm (CEST) 2.30pm-3.30pm (IST)

Friday October 17th: For North America (also Europe if late afternoon preferred)
Time: 10am-11am (PDT) 11am-12pm (CDT) 1pm-2pm (EDT) 6pm-7pm (BST - UK)

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Upcoming Webinar in October

The Keys to SystemC & TLM-2.0: How to be Successful
Date: Friday October 31st, 2014
Presenter: David C Black
Cost: FREE!
Summary: This webinar provides and introduction to SystemC, its best uses in the contexts of system modeling, hardware synthesis, and hardware verification and what you need to know to be successful using it.
Find out about this webinar and register

SystemC Webinar
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