LAST CHANCE TO REGISTER Easier UVM - Making Verification Methodology More Productive
Format: Webinar Date: Friday October 17th, 2014 Duration: 1 hour (with live Q&A) Presenter: John Aynsley Cost: FREE! Schedule: All time zones covered
In this webinar we give a short introduction to UVM, the Universal Verification Methodology for SystemVerilog, by taking advantage of Easier UVM, a set of coding guidelines and a code generator that creates UVM code compliant to those guidelines. Easier UVM is an effective way of learning and adopting UVM, and furthermore the Easier UVM guidelines and code generator are freely available for use. Easier UVM was created to help individuals and project teams learn and then become productive with UVM as quickly as possible.