Code Coverage as it relates to hardware design verification

In talking about both Code Coverage (fully automatic at least to start out with) and Functional Coverage (which involves the capture of properties to be tested/proven and/or the creation of coverage points/bins/crosses), it is nice to have an overview of Code Coverage.

I liked the following so far:

http://www.bullseye.com/coverage.html  (Not further shown here due to prominent threatening notices that suggest an overly-litigious author, but still, good content  :-) )

and this, as a high-level description:

http://www.aldec.com/en/solutions/functional_verification/code_coverage

"

Code Coverage

Code coverage is generated automatically from design source code. This verification metrics does not indicate correctness of your design – but measures how code is exercised while running regression test suites. If coverage is missing, it usually indicates either unused code or incomplete tests.

The following types of code coverage are available in Aldec Simulators:

• Statement coverage – examines each executable statement and counts the number of times it has been executed.
• Branch coverage – examines branches of each conditional statement and counts true or false conditions that have been met by a branch during simulation.
• Path coverage – examines the order of conditional statements execution and indicates whether all possible execution sequences have been verified by a testbench.
• Expression coverage – monitors logical expressions and indicates whether all possible states of a logical expression were exercised.
• Toggle coverage – monitors signals logic value changes and indicates signals that were not exercised properly by a testbench." ...