DVCon 2013 PlayList, verification et al, thanks to Shelf3D.com

Nice playlist for the design verification crowd:

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Play Playlist

13 Videos. Showing from #1

DVCon 2013 - Meirav Nitzan of Xilinx on her poster "A Smart Generation of Design Attributes" Meirav Nitzan of Xilinx R&D elaborates on her DVCon 2013 poster, "Taming the Beast: A Smart Generation of Design Attributes (Parameters) for Verification Closure Using Specman".	DVCon 2013 -- Neyaz Khan, Maxim, discusses mixed-signal (MS-SoC) verification In this interview Neyaz Khan, distinguished member of technical staff at Maxim, discusses best practices for mixed-signal SoC verification -- the topic of a DVCon 2013 paper he co-authored.	DVCon 2013: AXI Asynchronous Bridge Verification with AXI ABVIP and Formal Datapath Scoreboards An interview with presenter Chris Komar on the DVCon 2013 paper 2.1, "Overcoming AXI Asynchronous Bridge Verification Challenges with AXI Assertion-Based Verification IP (ABVIP) and Formal Datapath Scoreboards"
DVCon 2013: Saurabh Shrivastava of Xilinx on paper "How to Kill 4 Birds with 1 Stone Using Formal" Joseph Hupcey III speaks with Saurabh Shrivastava of Xilinx about his DVCon paper, "How to Kill 4 Birds with 1 Stone: In a Highly Configurable Design Using Formal to Validate Legal Configurations, Find Design Bugs, and Improve Testbench and Software Specifications" . (Authors: Saurabh Shrivastava, Kavita Dangi, Mukesh Sharma - Xilinx, Inc.; Darrow Chu - Cadence Design Systems, Inc.)	DVCon 2013: Best Practices in Verification Planning Co-author and presenter Paul Carzola shares some highlights of DVCon 2013 paper 4.2, "Best Practices in Verification Planning"	DVCon 2013 - Interview with AMIQ CEO Cristian Amitroaie Joseph Hupcey III speaks with Amiq CEO Cristian Amitroaie discuss trends in supporting the unavoidable mix of design & verification languages in simple work flows, and innovations supporting specific languages like SystemVerilog, e, and VHDL.
DVCon 2013 - Joseph Hupcey III speaks with James Pasco of STMicroelectronics	DVCon 2013 - Tutorial: Fast Track Your UVM Debug Productivity with Simulation and Acceleration Joe Hupcey III speaks with Nadav Chazan and Chris Dietrich of Cadence R&D about the DVCon tutorial "Fast Track Your UVM Debug Productivity with Simulation and Acceleration". Here Nadav and Chris outline some of the latest debug technologies and methodologies that increase the users' productivity and throughput -- in particular, how to combine the advantages of interactive and post-processing techniques.	DVCon 2013: Interview with Oski Technology CEO Vigyan Singhal Joseph Hupcey III speaks with Vigyan Singhal, the CEO of from formal and ABV specialist Oski Technology, about how careful advanced planning can substantially reduce risk in verification projects.
DVCon 2013 -- Mike Stellfox of Cadence discusses verification planning Mike Stellfox, Cadence fellow, discusses a DVCon panel he spoke at titled "Best Practices in Verification Planning."	DVCon 2013 -- John Biggs, IEEE 1801 chair, discusses new power format standard In this interview John Biggs, principal engineer at ARM and chair of the IEEE 1801 (Unified Power Format) working group, discusses the new IEEE 1801-2013 standard and notes additions and improvements.	DVCon 2013 -- Ziv Binyamini of Cadence comments on "million design starts" panel Ziv Binyamini, vice president and CTO of the System and Software Group at Cadence, comments on a panel he spoke at titled "Road to 1 Million Design Starts."
DVCon 2013 -- Stuart Swan of Cadence discusses high-level modeling In this interview Stuart Swan, senior architect at Cadence, discusses a methodology for using the same models for high-level synthesis and virtual prototyping. He spoke about this topic at a DVCon 2013 tutorial.

DVCon 2013 PlayList

'via Blog this'

Code Coverage as it relates to hardware design verification

In talking about both Code Coverage (fully automatic at least to start out with) and Functional Coverage (which involves the capture of properties to be tested/proven and/or the creation of coverage points/bins/crosses), it is nice to have an overview of Code Coverage.

I liked the following so far:

http://www.bullseye.com/coverage.html  (Not further shown here due to prominent threatening notices that suggest an overly-litigious author, but still, good content  :-) )

and this, as a high-level description:

http://www.aldec.com/en/solutions/functional_verification/code_coverage

"

Code Coverage

Code coverage is generated automatically from design source code. This verification metrics does not indicate correctness of your design – but measures how code is exercised while running regression test suites. If coverage is missing, it usually indicates either unused code or incomplete tests.

The following types of code coverage are available in Aldec Simulators:

• Statement coverage – examines each executable statement and counts the number of times it has been executed.
• Branch coverage – examines branches of each conditional statement and counts true or false conditions that have been met by a branch during simulation.
• Path coverage – examines the order of conditional statements execution and indicates whether all possible execution sequences have been verified by a testbench.
• Expression coverage – monitors logical expressions and indicates whether all possible states of a logical expression were exercised.
• Toggle coverage – monitors signals logic value changes and indicates signals that were not exercised properly by a testbench." ...

Verification Planning and management, on Verification Academy, coverage strategy overviews (somewhat System-Verilog centric)

Verification Planning and Management

The verification of any design of size is a daunting task that requires successful forethought in the form of formulating, architecting, strategizing and documenting an overall verification blueprint. The value of creating such a blueprint at the start of a project has been proven out through gathered metrics of successful projects. This verification planning and management (VPM) course is a 3 part, 90 min introduction towards creating such a verification blueprint.

The goal of verification planning and management is to architect an overall verification approach, and then to document that approach in a family of useful, easily extracted, maintainable verification documents that will strategically guide the overall verification effort so that the most amount of verification is accomplished in the allotted time. The aim of this course is to define terms, logically divide up the verification effort, and lay the foundation for actual verification planning and management on a real project. This material is introductory only, as it is a modification of the first few presentations an entire set of over 20 VPM presentations/discussions that are custom applied to an actual project where they guide the creation of verification documentation and implementation.

You are encouraged to first view Evolving Verification Capabilities by Harry Foster that provides the framework for all of the Academy courses.

---

Peet James

Planning, Measurement, and Analysis

Crawl

Sessions

Why Plan?

This session moves beyond general fear based justifications for increased verification efforts to logical reasons for why verification typically is more overall effort than the actual design.

Why It's Hard

This session covers seven historical reasons as to why the overall verification effort and verification planning in general is difficult.

Plan of Attack

This session goes towards dividing up all that work into some logical categories and coming up with a plan of attack for overall verification success.

https://verificationacademy.com/courses/verification-planning-and-management