Showing posts with label Accellera. Show all posts
Showing posts with label Accellera. Show all posts

Friday, July 27, 2012

Download SystemC - Accellera

SystemC - Accellera Systems Initiative:

Download SystemC

Standards are developed in a collaborative and open environment by technical working groups. Working groups operate by building consensus regarding requirements, proposed new features, and implementation. Ultimately these may become part of a future standard. Participation in the technical working groups is the primary way that progress is made in improving the SystemC language, implementation, and associated libraries.

Download Standards

Current Releases

ItemFilenameDetailsSizeDate Modified
SystemC 2.3 (Includes TLM)systemc-2.3.0.tgzCore SystemC Language and Examples, Release 2.3
Status: Active; Maturity: Stable
7,209,2332012-07-02
systemc_regressions-2.3.0.tgz2,361,9162012-07-02
AMS 1.0

OSCI_SystemC_AMS_extensions _1v0_Standard.zipAnalog/Mixed-signal (AMS) Extensions, Release 1.0
Status: Active; Maturity: Stable
5,401,6882010-03-05
More AMS information and FAQ

Previous Releases

...

Open-Source SystemC Library, Simulator Provide Insights Into New IEEE 1666 Standard

Comments(0)Filed under: Industry Insights, SystemC, OSCI, TLM, Accellera, process control, IEEE 1666, open source, TLM 2.0, David Black, Stan Krolikoski, IEEE 1666-2011, proof of concept, SystemC simulator, SystemC libraryThere is no better way to learn about the IEEE 1666-2011 SystemC standard than to use it - and the Accellera Systems Initiative has provided an easy way to do that with version 2.3.0 of its SystemC open-source "proof of concept" library. This free offering makes it possible to create SystemC models and it includes a simulation kernel that can execute them.
The new library is essentially the latest version of the free SystemC simulator that was offered by the Open SystemC Initiative (OSCI) before its merger with Accelleralast year. "This is kind of a starting point for many folks," said David Black, chair of the Accellera Systems Initiative SystemC Language Working Group and Senior Member of Technical Staff at training firm Doulos. "It makes SystemC more widely available to a larger group of users."
The 2.3.0 library gives prospective users of the latest SystemC revision the opportunity to start experimenting with the new features right away, and Doulos has contributed a presentation to the kit to help explain the new features. IEEE 1666-2011 was approved in late 2011. One important new feature is the inclusion of the OSCI transaction-level modeling (TLM) standards into the SystemC Language Reference Manual. Consequently, with the 2.3.0 SystemC library, users can obtain both SystemC and OSCI TLM 2.0 by downloading one file.
Here are some other new features included in the 2.3.0 library:

  • Process control constructs that make it possible for one process to suspend, resume, disable, or enable another (see blog post here for details)
  • A first-class events list and a new container for SystemC objects that simplify the description of generic and scalable models
  • An improved simulation API and a new thread safety mechanism that will allow support for multi-threading
  • A new document that highlights the features of the latest SystemC standard
  • Reorganized documentation for clarity
While the library can be used to create and execute SystemC models, it is not a commercial simulation environment. As Black noted, commercial simulators may add such features as sophisticated debugging, performance improvements, bug fixes, ease of use, lint checks, and co-simulation with RTL, not to mention support.
The proof-of-concept library and simulator "is useful as a quick and dirty way to gain some insights into the new SystemC standard," said Stan Krolikoski, Accellera Systems Initiative secretary and distinguished engineer at Cadence. "However, it is insufficient for real-world application because SoC design and verification need debug, RTL integration, and support that can come only from commercial tools. It [library] is a good reference for very good standards work, but users do need more for robust SoC applications."
Want to know more? You can follow the links below.
Richard Goering

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Friday, June 1, 2012

Video tutorial: UVM, Ready, Set, Deploy, thanks to Accellera

Home - Accellera Systems Initiative:

http://www.accellera.org/news/videos/uvmreadysetdeploy

New Video Tutorial – UVM: Ready, Set, Deploy!

It’s been six months since Accellera and the Open SystemC Initiative joined forces to become Accellera Systems Initiative. In that time, we have achieved several milestones in developing standards that address the real needs of system and semiconductor designers.
The Universal Verification Methodology (UVM) standard continues to gain adoption across the verification community. Presented by expert verification methodology architects and engineers at DVCon 2012, the eight-part video tutorial is available at no cost to users and provides an introduction to key UVM concepts and best practices.
See us at the Design Automation Conference, June 4-7 in San Francisco! We will be hosting several events at this year's DAC including a luncheon on the Unified Coverage Interoperability Standard (UCIS), NASCUG meeting, and special birds-of-a-feather sessions. At the luncheon, Accellera Systems Initiative will receive the Tenzing Norgay Award, and will present its 2012 Leadership Award. Events are no charge with advance registration required. Read the latest article on UCIS featured in our newsletter.

Dennis Brophy Receives 2012 Accellera Systems Initiative Leadership Award 

To be presented at our luncheon at DAC in San Francisco on Wednesday, June 6, 2012
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Recent Happenings


 • UVM 1.1b Reference Implementation now available

• Accellera Systems Initiative receives 2012 Tenzing Norgay Award from Synopsys. See press release >

• May newsletter now available.

• John Aynsley receives the 2012Technical Excellence Award.
  
• IEEE 1666-2011 Now Available for Free Download courtesy of Accellera Systems Initiative.

• Open Verification Library (OVL) 2.6release is now available for download.


OSCI and Accellera Unite

The new organization will leverage the complementary efforts of both groups to create more comprehensive standards.




News

Featured Quote

"We continue to work with the IEEE to make approved EDA and IP standards available," said Shishpal Rawat, chair of Accellera Systems Initiative. "Through the IEEE Get Program, we provide valuable standards documentation at no cost to the worldwide electronics industry community to support and foster electronic design innovation."... More »

Other News From the Industry



Synopsys Honors Accellera Systems Initiative with 2012 Tenzing Norgay Interoperability Achievement Award
Open SystemC Initiative and Accellera merger paves way for broad interoperability standards
MOUNTAIN VIEW, Calif., May 24, 2012 -- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, announced that Accellera Systems Initiative will receive Synopsys’ twelfth annual Tenzing Norgay Interoperability Achievement Award for advancing industry standards that enable interoperable system design flows. More »

Featured Videos


UVM: Ready, Set, Deploy!

Accellera Systems Initiative UpdateUVM - Ready, Set, Deploy

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Monday, April 2, 2012

NASCUG 17 (DVCON '12) SystemC Presentations Now Available, see links

17th NASCUG Meeting Agenda


17th NASCUG Meeting

27 February 2012

8:30 - 9:00 AMRegistration
9:00 - 9:10 AMWelcome, Agenda & NASCUG IntroductionTor Jeremiassen, Texas Instruments, USA
9:10 - 9:25 AMAccellera Systems Initiative UpdateShishpal Rawat, Chairman, Accellera Systems Initiative
View presentation
9:25 - 9:55 AMRoundtable: Leveraging Synergy: Future Opportunities with SystemCModerated by Ed Sperling, System Level Design
9:55 - 10:20 AMWhat does C++2011 mean to SystemC?David C Black, Doulos, USA
View presentation
View details
10:20 - 10:45 AMSynchronization between a SystemC-based Off-line Restbus Simulator and a Hardware-In-the-Loop FlexRay NetworkGilles Bertrand Defo, University Of Paderborn, Germany
View presentation
View details
10:45 - 10:55 AMBreak
10:55 - 11:20 AMExtending Fixed Sub-systems at the TLM Level - Experiences from the FPGA WorldFrank Schirrmeister, Cadence, USA
View presentation
View details
11:20 - 11:45 AMA Generic Language for Hardware & Software, Are We There Yet? An Explorative Case Study Examining the Usage of SystemC for Multicore ProgrammingSushil Menon, University of Pennsylvania, USA
View presentation
View details
11:45 AM - NOONClosing Remarks and Prize Drawing 
Jack Donovan, Duolog, UK


Abstracts

What does C++2011 mean to SystemC?

In September of 2011, ISO approved an update to the C++ standard, which is known variously as ISO/IEC 14882:2011, C++0x and C++11. This presentation will take a quick look at some of the features and illustrate how they could change the way we write code. Discussion will also include potential impacts to performance and code quality. Code examples will be given with comments on experiences using the new features and what limitations were encountered.

Synchronization between a SystemC-based Off-line Restbus Simulator and a Hardware-In-the-Loop FlexRay Networ

Residual bus simulation (restbussimulation) is a method used in particular for the design of automotive software typically consisting of distributed controller nodes communicating via a bus. A typical use case is the integration of newly developed functionality (features) into an existing system. To achieve this, the residual bus simulator has to provide messages from non-existing ECUs to the rest of the system at runtime. This enables the test and/or validation of new functionality in an early stage of the development process by means of simulation.
In this paper we present an approach for synchronization between an off-line residual bus simulator implemented in SystemC and a Hardware-In-the-Loop (HIL) system. The residual bus simulator encapsulates functional SystemC models of non-existing nodes. Due to the lack of the real-time simulation support of SystemC, not all the data generated by physical nodes might be received and processed "on time" by the residual bus simulator as the execution speed and order of the SystemC processes can vary. Furthermore our approach makes use of a special downsampling method. During the downsampling process special data such as peaks are detected and can either be ignored or processed. The evaluation of our approach was conducted using a steer-by-wire demonstrator.

Extending Fixed Sub-systems at the TLM Level - Experiences from the FPGA World

One of the most interesting steps of progress towards effective SystemC based system-level design and emphasis on the importance of embedded software has recently come from the world of FPGAs, making available devices combining programmable logic of up to several million ASIC gate equivalents with hard implementations of ARM Cortex-A9 based multiprocessor sub-systems.
The Xilinx Zynq platform encourages extensibility with user logic at the TLM level by offering an "Extensible Virtual Platform", which means design teams can create using custom SystemC models a virtual prototype for software development even before the RTL of the user defined logic is developed, either by hand or using high-level synthesis.
This presentation will report on the user experiences of extending at the TLM level a fixed SystemC based sub-system with user logic which is eventually to be mapped into the programmable FPGA fabric. We will quantify the value of extending a platform like Zynq at the transaction-level by comparing design flows with and without usage of TLM models.

A Generic Language for Hardware & Software, Are We There Yet? An Explorative Case Study Examining the Usage of SystemC for Multicore Programming

The recent migration from uniprocessor systems to multicore hardware-architectures has coerced the invention of effective tools that alleviate the process of developing concurrent software. Whereas the software industry has channelized its efforts into the development of open-source standardizations such as OpenMP, the increasing adoption of system-level design methodologies has provided designers with a multitude of tools, SystemC being one such which enables hardware-software codesign and permits the modeling of concurrency.
In this paper, we examine both approaches through a comparative study of the process of developing concurrent software using OpenMP and SystemC. Specifically, we choose to implement the Quicksort algorithm, as it is easily parallelizable and hence illustrates properties that resemble that of typical concurrent software. We first showcase the process of modeling a concurrent version of Quicksort, and then discuss its implementations using OpenMP and SystemC. We then compare the performance (execution-time and execution-speedup) and ease of implementation of the variants, including a sequential implementation of Quicksort. Experimental results suggest that although it permits the development of concurrent software, due to performance issues, SystemC does not seem to be a suitable platform for multicore programming.


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Monday, March 12, 2012

SystemC Events at DATE 2012, courtesy of Accellera

From: Accellera Systems Initiative
Date: Mon, Mar 12, 2012 at 2:28 PM
Subject: SystemC Events at DATE 2012


accellera.org

Join Us for SystemC Events at DATE 2012
Design, Automation & Test in Europe Conference

   


Maritim Hotel & Internationales Congress Center
Dresden, Germany
www.date-conference.com


Workshop: OSCI and Accellera Core Technologies for the Next Generation of System-Level Design

Friday, March 16, 2012
8:30h - 16:30h, Room: Konferenz 4
www.date-conference.com/conference/session/W6

You may register on-site at ICC Dresden, Ostra-Ufer 2, Dresden, Germany.
The merger of the Open SystemC Initiative (OSCI) and Accellera to the Accellera Systems Initiative (ASI) unifies trend-setting standardization activities in the Electronic Design Automation (EDA) world and opens a wide range of new perspectives and synergies. The standards that are established and promoted by OSCI and Accellera cover a broad spectrum of today's and tomorrow's Electronic System Level (ESL) modeling and verification strategies.
This workshop is focused on the core technologies from both the OSCI and the Accellera world, and gives an outlook on how techniques may collaborate and converge. The format of the workshop includes four invited sessions from Doulos, Synopsys, Cadence, and VWorks providing a substantiated overview of the technologies and their future way-providing a practical guide on how those technologies can be successfully applied for improving a companies' design strategy. Five user sections from XMOS, Sonics and Lantiq, the U Bremen, Bosch, and the Worcester Polytechnic Institute complement these core sections. They provide insights into the application and the development in research and industrial domains.
Agenda
08:30      Welcome & Opening
Wolfgang Rosenstiel, U Tuebingen & ESCUG, DE
08:40 Core Section 1: Doulos
IEEE 1666-2011 SystemC Standard
John Aynsley, Doulos, U.K.
09:40 User Section 1:
Using SystemC with XMOS Devices
David Lacey, XMOS, U.K.
10:10 Coffee Break
10:30 Core Section 2: Synopsys
TLM-2.0 Technology for Off-Chip Interfaces
Victor Reyes, Synopsys, US
11:30 User Section 2:
SoC performance evaluation using high performance SystemC and TLM models for communications SoCs
Rocco Jonack, Sonics, US Bernhard Keppler, Lantiq, DE Renate Henftling, Lantiq, DE
12:00 Lunch Break
13:00 Core Section 3: Cadence
Virtual Prototypes for Embedded Software Verification
Markus Winterholer, Cadence, DE, Leonard Drucker, Cadence, US
14:00 User Section 3:
SystemC-based ESL Verification Flow Integrating Property Checking and Automatic Debugging
Hoang M. Le, Daniel Grosse, Rolf Drechsler, U Bremen and DFKI, DE
14:30 Coffee Break
14:50 Core Section 4: VWorks
Programmable Debug of Linux/Android OS on Virtual PLatforms
Jay Yantchev, VWorks, AU
15:50 User Section 4:
Using IP-XACT to ease system development with SystemC/TLM The Transparent TLM (TTLM) Approach
Simon Hufnagel, Bosch, DE, Christoph Grimm, Vienna U Technology, AT
16:20 User Section 5:
System-Level Post-Manufacturing Testing
Zainalabedin Navabi, Worcester Polytechnic Institute, US
16:50 Closing
Wolfgang Rosenstiel, U Tuebingen & ESCUG, DE

 


European SystemC User's Group 25

Tuesday, March 13, 2012
18:30h - 21:30h, Room Konferenz 2
www.ti.uni-tuebingen.de/escug

The European SystemC User's Group (ESCUG) celebrates its 25th meeting at the DATE (Design Automation & Test in Europe) 2012 Conference on March 13, 2012. This meeting will be organized as a panel discussion around the merger of OSCI and Accellera, and its opportunities and challenges.
Moderator: Gary Smith, Gary Smith EDA, US
Panelists:
  • Marcello Coppola, ST Microelectronics, FR
  • Grant Martin, Tensilica, US
  • John Aynsley, Doulos, UK
  • Dennis Brophy, Mentor Graphics, US
  • Josef Eckmueller, Intel, DE
  • Johannes Stahl, Synopsys, US
  • Stan Krolikoski, Cadence, US
Closing: Wolfgang Rosenstiel, University of Tuebingen & ESCUG, DE
Note that the number of seats is limited and registration will be handled on a first-come first-served basis. Participation is free of charge.

 


ESCUG Sponsors

Accellera Systems Initiative, 1370 Trancas Street, #163, Napa, CA 94558

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Thursday, March 1, 2012

Nice DVCon explanation from Peggy Aycinena, sorry it's late (there's always next year)

EDACafe.com - What Would Joe Do? - DVCon: You will be Tested

DVCon: You will be Tested

February 10th, 2012 by Peggy Aycinena
Pay close attention. You will be tested on the following.
DVCon stands for Design & Verification Conference. Not surprisingly, it’s targeted at design and verification engineers. Despite rumors on the street, design and verification engineers are still two different types of employees, particularly at the big design houses. That’s why DVCon is applicable to both. Two disciplines. One conference.
DVCon happens every year around this time at the Double Tree Inn in San Jose. Approximately 700 people attend. The conference is 4 days long, including 2 days of tutorials on either side of 2 days of technical sessions. There’s always one major panel, this year on February 28th, that showcases industry execs. Famously, it used to be moderated by John Cooley. Now it’s moderated by JL Gray, who is also famous.
JL’s panel this year will include Ted Vucurevich, John Costello (sic erat scriptum), Gary Smith, andJim Hogan. If you do not know who these people are, perhaps you should not be coming to DVCon. Unless you’re a design or verification engineer, in which case that’s okay. You’ll probably know someone on the panel the next day hosted by Brian Bailey, who is not famous. He is legendary. Brian’s panel is about Hardware-Assisted Verification and includes people from Qualcomm, ARM,SpringSoft, Xilinx, and Cadence.
DVCon also has a major keynote, this year on February 29th, which features the CEO of one of the Big 3 EDA companies. Last year it was Mentor’s Wally Rhines. This year it’s Synopsys’ Aart de Geus. His talk is entitled: Principles for Success in IC Design. DVCon is well known for this type of positive thinking. Last year, JL Gray’s panel was entitled: Making Great Products Great. This year it’s entitled: The Resurgence of Chip Design. You will not find a keynote at DVCon entitled:Principles for Failure in IC Design, nor a panel entitled: Making Great Products Lousy. That kind of thinking is not what DVCon is all about.
DVCon is sponsored these days by Accellera Systems Initiative, a single organization created last year out of two separate organizations, Accellera and OSCI. That’s because both organizations are interested in system-level design. NASCUG is also interested in system-level design. It too has a presence at DVCon. If you don’t know what NASCUG means, click here. Meanwhile, remember that Accellera was itself created in 2000 out of two separate organizations, OVI and VHDL International. This type of thing is also what DVCon is all about. People helping people make their organizations better. People helping people figure out how we can all get along.
Creating standards is another way of figuring out how we can all get along. Which brings us toKaren Bartleson. Like Accellera Systems Initiative, Bartleson is a single person who represents two complementary ideas: Standards and Positive Thinking. This is why Karen is the perfect person to be General Chair of DVCon. She is Synopsys’ go-to person for all things related to Standards, and she is nothing, if not all about Positive Thinking. Add these together, and multiply by two, and you see why this is the second year in a row that Karen has been DVCon General Chair.
Karen will not be General Chair next year. She will be busy doing something else. She will be serving as President of the IEEE Standards Association, overseeing 900 different standards and the 15,000 people who maintain and update those standards. Maybe she could invite all of those people to DVCon in 2013, although it might get a little crowded if they all came. MP Associates, the folks who run DVCon (and DAC among other things), might run out of conference bags. Nonetheless, MP Associates is a very capable organization. If Karen Bartleson got all 15,000 IEEE standards committee members to come to DVCon next year, I’m sure that MP Associates would be up to the task.
Speaking of people who like people, that brings us to the idea of networking, wine/beer, and exhibit halls. DVCon serves up a generous dollop of all three, along with the tutorials, keynotes, panels, and technical sessions. I have checked with Karen Bartleson and she assures me that when the DVCon 2012 Exhibit Hall is open – February 28th from 3:30 to 6:30 pm, and February 29thfrom 4:00 to 7:00 pm – there will be lots of networking, food, wine/beer, and sanctioned recruiting amidst the 30+ exhibitor booths.
She also emphasized that the wine/beer will be complementary to all attendees. That might be a tall order for next year if 15,000 people come to DVCon. All the more reason why you should beplanning to come this year. Serving up wine and hors d’oeuvres to 700 people is an order of magnitude easier than serving same to 15,000. Even if highly capable MP Associates could pull it off. Or if DVCon organizers could afford it.
Speaking of money, DVCon is good there as well. They have made enough money to be profitableseveral years in a row. Accellera Systems Initiative, apparently, also has some extra money because they will be presenting a monetary award to the Best Paper winners at DVCon. Yet another reason to attend. The Best Paper selection will be done by the attendees themselves, voting throughout the conference to determine who will be announced Big Winner in the last session on February 29th. Karen said receiving Best Paper at DVCon is something special, particularly given the quality of the papers submitted.
Okay, if you’ve read carefully to this point, there’s only three things left to do.
* Register for DVCon.
* Watch Karen Bartleson’s upcoming Conversation Central interview with the DVCon 2012Technical Program Chair and Tutorials & Panel Chair on February 16th.
* Take the quiz, which will be posted here on February 17th.
*************************

EDACafe.com - What Would Joe Do? - DVCon: You will be Tested

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