Video tutorial: UVM, Ready, Set, Deploy, thanks to Accellera

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New Video Tutorial – UVM: Ready, Set, Deploy!

It’s been six months since Accellera and the Open SystemC Initiative joined forces to become Accellera Systems Initiative. In that time, we have achieved several milestones in developing standards that address the real needs of system and semiconductor designers.

The Universal Verification Methodology (UVM) standard continues to gain adoption across the verification community. Presented by expert verification methodology architects and engineers at DVCon 2012, the eight-part video tutorial is available at no cost to users and provides an introduction to key UVM concepts and best practices.

See us at the Design Automation Conference, June 4-7 in San Francisco! We will be hosting several events at this year's DAC including a luncheon on the Unified Coverage Interoperability Standard (UCIS), NASCUG meeting, and special birds-of-a-feather sessions. At the luncheon, Accellera Systems Initiative will receive the Tenzing Norgay Award, and will present its 2012 Leadership Award. Events are no charge with advance registration required. Read the latest article on UCIS featured in our newsletter.

Dennis Brophy Receives 2012 Accellera Systems Initiative Leadership Award 

To be presented at our luncheon at DAC in San Francisco on Wednesday, June 6, 2012

Details >>>

DAC 2012

June 6 | San Francisco, CA

• Hosted Luncheon and UCIS Technical Presentation
• Birds-of-a-Feather Meetings
• NASCUG XVIII

Find out more >

SystemC Japan

July 6 | Yokohama, Japan

DVCon 2013

Call for abstracts >

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Recent Happenings  • UVM 1.1b Reference Implementation now available • Accellera Systems Initiative receives 2012 Tenzing Norgay Award from Synopsys. See press release > • May newsletter now available. • John Aynsley receives the 2012Technical Excellence Award.    • IEEE 1666-2011 Now Available for Free Download courtesy of Accellera Systems Initiative. • Open Verification Library (OVL) 2.6release is now available for download. OSCI and Accellera Unite The new organization will leverage the complementary efforts of both groups to create more comprehensive standards. • Welcome from the Chair  • Read what Accellera Systems Initiative members and others are saying • Frequently Asked Questions

News Dennis Brophy to Receive Accellera Systems Initiative Leadership Award 30 May 2012 Accellera Systems Initiative Hosts User Events at the 2012 Design Automation Conference 23 May 2012 ISCUG 2012 Slated for April 9-10 in Bangalore 29 Mar 2012 Featured Quote "We continue to work with the IEEE to make approved EDA and IP standards available," said Shishpal Rawat, chair of Accellera Systems Initiative. "Through the IEEE Get Program, we provide valuable standards documentation at no cost to the worldwide electronics industry community to support and foster electronic design innovation."... More » Other News From the Industry Synopsys Honors Accellera Systems Initiative with 2012 Tenzing Norgay Interoperability Achievement Award Open SystemC Initiative and Accellera merger paves way for broad interoperability standards MOUNTAIN VIEW, Calif., May 24, 2012 -- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, announced that Accellera Systems Initiative will receive Synopsys’ twelfth annual Tenzing Norgay Interoperability Achievement Award for advancing industry standards that enable interoperable system design flows. More »

Featured Videos UVM - Ready, Set, Deploy

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NASCUG 17 (DVCON '12) SystemC Presentations Now Available, see links

17th NASCUG Meeting Agenda

17th NASCUG Meeting

27 February 2012

8:30 - 9:00 AM	Registration
9:00 - 9:10 AM	Welcome, Agenda & NASCUG IntroductionTor Jeremiassen, Texas Instruments, USA
9:10 - 9:25 AM	Accellera Systems Initiative UpdateShishpal Rawat, Chairman, Accellera Systems Initiative View presentation
9:25 - 9:55 AM	Roundtable: Leveraging Synergy: Future Opportunities with SystemCModerated by Ed Sperling, System Level Design
9:55 - 10:20 AM	What does C++2011 mean to SystemC?David C Black, Doulos, USA View presentation View details
10:20 - 10:45 AM	Synchronization between a SystemC-based Off-line Restbus Simulator and a Hardware-In-the-Loop FlexRay NetworkGilles Bertrand Defo, University Of Paderborn, Germany View presentation View details
10:45 - 10:55 AM	Break
10:55 - 11:20 AM	Extending Fixed Sub-systems at the TLM Level - Experiences from the FPGA WorldFrank Schirrmeister, Cadence, USA View presentation View details
11:20 - 11:45 AM	A Generic Language for Hardware & Software, Are We There Yet? An Explorative Case Study Examining the Usage of SystemC for Multicore ProgrammingSushil Menon, University of Pennsylvania, USA View presentation View details
11:45 AM - NOON	Closing Remarks and Prize Drawing  Jack Donovan, Duolog, UK

Abstracts

What does C++2011 mean to SystemC?

In September of 2011, ISO approved an update to the C++ standard, which is known variously as ISO/IEC 14882:2011, C++0x and C++11. This presentation will take a quick look at some of the features and illustrate how they could change the way we write code. Discussion will also include potential impacts to performance and code quality. Code examples will be given with comments on experiences using the new features and what limitations were encountered.

Synchronization between a SystemC-based Off-line Restbus Simulator and a Hardware-In-the-Loop FlexRay Networ

Residual bus simulation (restbussimulation) is a method used in particular for the design of automotive software typically consisting of distributed controller nodes communicating via a bus. A typical use case is the integration of newly developed functionality (features) into an existing system. To achieve this, the residual bus simulator has to provide messages from non-existing ECUs to the rest of the system at runtime. This enables the test and/or validation of new functionality in an early stage of the development process by means of simulation.

In this paper we present an approach for synchronization between an off-line residual bus simulator implemented in SystemC and a Hardware-In-the-Loop (HIL) system. The residual bus simulator encapsulates functional SystemC models of non-existing nodes. Due to the lack of the real-time simulation support of SystemC, not all the data generated by physical nodes might be received and processed "on time" by the residual bus simulator as the execution speed and order of the SystemC processes can vary. Furthermore our approach makes use of a special downsampling method. During the downsampling process special data such as peaks are detected and can either be ignored or processed. The evaluation of our approach was conducted using a steer-by-wire demonstrator.

Extending Fixed Sub-systems at the TLM Level - Experiences from the FPGA World

One of the most interesting steps of progress towards effective SystemC based system-level design and emphasis on the importance of embedded software has recently come from the world of FPGAs, making available devices combining programmable logic of up to several million ASIC gate equivalents with hard implementations of ARM Cortex-A9 based multiprocessor sub-systems.

The Xilinx Zynq platform encourages extensibility with user logic at the TLM level by offering an "Extensible Virtual Platform", which means design teams can create using custom SystemC models a virtual prototype for software development even before the RTL of the user defined logic is developed, either by hand or using high-level synthesis.

This presentation will report on the user experiences of extending at the TLM level a fixed SystemC based sub-system with user logic which is eventually to be mapped into the programmable FPGA fabric. We will quantify the value of extending a platform like Zynq at the transaction-level by comparing design flows with and without usage of TLM models.

A Generic Language for Hardware & Software, Are We There Yet? An Explorative Case Study Examining the Usage of SystemC for Multicore Programming

The recent migration from uniprocessor systems to multicore hardware-architectures has coerced the invention of effective tools that alleviate the process of developing concurrent software. Whereas the software industry has channelized its efforts into the development of open-source standardizations such as OpenMP, the increasing adoption of system-level design methodologies has provided designers with a multitude of tools, SystemC being one such which enables hardware-software codesign and permits the modeling of concurrency.

In this paper, we examine both approaches through a comparative study of the process of developing concurrent software using OpenMP and SystemC. Specifically, we choose to implement the Quicksort algorithm, as it is easily parallelizable and hence illustrates properties that resemble that of typical concurrent software. We first showcase the process of modeling a concurrent version of Quicksort, and then discuss its implementations using OpenMP and SystemC. We then compare the performance (execution-time and execution-speedup) and ease of implementation of the variants, including a sequential implementation of Quicksort. Experimental results suggest that although it permits the development of concurrent software, due to performance issues, SystemC does not seem to be a suitable platform for multicore programming.

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Magma Assimilation, Forte (news + jobs), DVcon, Specman e, Atrenta, Calypto

If you care at all about EDA and verification, you should definitely get on John Cooley's mailing list.  Good stuff!

Cheers,
Connie "I Was Assimilated by Cadence, But I Got Better" O'Dell
Sr. Verification Specialist
c.odell@co-consulting.net
303-641-5191
_____________________________________________
CO Consulting - Boulder, CO - http://co-consulting.net

---------- Forwarded message ----------
From: John Cooley
Date: Thu, Mar 8, 2012 at 3:32 AM
Subject: TSMC 28 nm, DVcon, Specman e, Atrenta, Calypto, Forte, SKILL

 "I feel bad for the Magma employees being absorbed by the
  Synopsys Borg.  Today they learn that resistance is futile."

      - An EDA Vendor on SNPS-LAVA merger completing

-------------------------------------------------

 HW forums cite rumor that TSMC suddenly halted 28 nm production
    http://www.deepchip.com/items/0500-01.html

 Brett's quickie trip reports on both DVcon'12 and NASCUG'12 confs
    http://www.deepchip.com/items/0500-02.html

 CDNS too afraid of SV sales to support SNPS/MENT Specman "e"
    http://www.deepchip.com/items/0500-03.html

 Three chip designers hands-on evals of Atrenta Spyglass Power
    http://www.deepchip.com/items/0500-04.html

 We cut another 9% of power using the Calypto RTL PowerPro tool
    http://www.deepchip.com/items/0500-05.html

 Shiv compares IC Manage, CVS, and Subversion for digital design
    http://www.deepchip.com/items/0500-06.html

 I designed a USB 3.0 core using SystemC and Forte Cynthesizer
    http://www.deepchip.com/items/0500-07.html

 Huh? SKILL sklint() already built into the Virtuoso environment
    http://www.deepchip.com/items/0500-08.html

-------------------------------------------------

 Docea Power to unveil AceThermalModeler at upcoming DATE'12
    http://www.deepchip.com/look/see120308-01.html

 Jasper CEO Kathryn Kranen in San Jose Mercury News interview
    http://www.deepchip.com/look/see120308-02.html

 San Jose, CA - Forte seeks SystemC Cynthesizer field engineers
     http://www.deepchip.com/jobs/033.html

Nice DVCon explanation from Peggy Aycinena, sorry it's late (there's always next year)

EDACafe.com - What Would Joe Do? - DVCon: You will be Tested

DVCon: You will be Tested

February 10th, 2012 by Peggy Aycinena

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Pay close attention. You will be tested on the following.
DVCon stands for Design & Verification Conference. Not surprisingly, it’s targeted at design and verification engineers. Despite rumors on the street, design and verification engineers are still two different types of employees, particularly at the big design houses. That’s why DVCon is applicable to both. Two disciplines. One conference.
DVCon happens every year around this time at the Double Tree Inn in San Jose. Approximately 700 people attend. The conference is 4 days long, including 2 days of tutorials on either side of 2 days of technical sessions. There’s always one major panel, this year on February 28th, that showcases industry execs. Famously, it used to be moderated by John Cooley. Now it’s moderated by JL Gray, who is also famous.
JL’s panel this year will include Ted Vucurevich, John Costello (sic erat scriptum), Gary Smith, andJim Hogan. If you do not know who these people are, perhaps you should not be coming to DVCon. Unless you’re a design or verification engineer, in which case that’s okay. You’ll probably know someone on the panel the next day hosted by Brian Bailey, who is not famous. He is legendary. Brian’s panel is about Hardware-Assisted Verification and includes people from Qualcomm, ARM,SpringSoft, Xilinx, and Cadence.
DVCon also has a major keynote, this year on February 29th, which features the CEO of one of the Big 3 EDA companies. Last year it was Mentor’s Wally Rhines. This year it’s Synopsys’ Aart de Geus. His talk is entitled: Principles for Success in IC Design. DVCon is well known for this type of positive thinking. Last year, JL Gray’s panel was entitled: Making Great Products Great. This year it’s entitled: The Resurgence of Chip Design. You will not find a keynote at DVCon entitled:Principles for Failure in IC Design, nor a panel entitled: Making Great Products Lousy. That kind of thinking is not what DVCon is all about.
DVCon is sponsored these days by Accellera Systems Initiative, a single organization created last year out of two separate organizations, Accellera and OSCI. That’s because both organizations are interested in system-level design. NASCUG is also interested in system-level design. It too has a presence at DVCon. If you don’t know what NASCUG means, click here. Meanwhile, remember that Accellera was itself created in 2000 out of two separate organizations, OVI and VHDL International. This type of thing is also what DVCon is all about. People helping people make their organizations better. People helping people figure out how we can all get along.
Creating standards is another way of figuring out how we can all get along. Which brings us toKaren Bartleson. Like Accellera Systems Initiative, Bartleson is a single person who represents two complementary ideas: Standards and Positive Thinking. This is why Karen is the perfect person to be General Chair of DVCon. She is Synopsys’ go-to person for all things related to Standards, and she is nothing, if not all about Positive Thinking. Add these together, and multiply by two, and you see why this is the second year in a row that Karen has been DVCon General Chair.
Karen will not be General Chair next year. She will be busy doing something else. She will be serving as President of the IEEE Standards Association, overseeing 900 different standards and the 15,000 people who maintain and update those standards. Maybe she could invite all of those people to DVCon in 2013, although it might get a little crowded if they all came. MP Associates, the folks who run DVCon (and DAC among other things), might run out of conference bags. Nonetheless, MP Associates is a very capable organization. If Karen Bartleson got all 15,000 IEEE standards committee members to come to DVCon next year, I’m sure that MP Associates would be up to the task.
Speaking of people who like people, that brings us to the idea of networking, wine/beer, and exhibit halls. DVCon serves up a generous dollop of all three, along with the tutorials, keynotes, panels, and technical sessions. I have checked with Karen Bartleson and she assures me that when the DVCon 2012 Exhibit Hall is open – February 28th from 3:30 to 6:30 pm, and February 29thfrom 4:00 to 7:00 pm – there will be lots of networking, food, wine/beer, and sanctioned recruiting amidst the 30+ exhibitor booths.
She also emphasized that the wine/beer will be complementary to all attendees. That might be a tall order for next year if 15,000 people come to DVCon. All the more reason why you should beplanning to come this year. Serving up wine and hors d’oeuvres to 700 people is an order of magnitude easier than serving same to 15,000. Even if highly capable MP Associates could pull it off. Or if DVCon organizers could afford it.
Speaking of money, DVCon is good there as well. They have made enough money to be profitableseveral years in a row. Accellera Systems Initiative, apparently, also has some extra money because they will be presenting a monetary award to the Best Paper winners at DVCon. Yet another reason to attend. The Best Paper selection will be done by the attendees themselves, voting throughout the conference to determine who will be announced Big Winner in the last session on February 29th. Karen said receiving Best Paper at DVCon is something special, particularly given the quality of the papers submitted.
Okay, if you’ve read carefully to this point, there’s only three things left to do.
* Register for DVCon.
* Watch Karen Bartleson’s upcoming Conversation Central interview with the DVCon 2012Technical Program Chair and Tutorials & Panel Chair on February 16th.
* Take the quiz, which will be posted here on February 17th.
*************************

Tags: Aart de Geus, Accellera Systems Initiative, Brian Bailey, DVCon, JL Gray, Karen Bartleson,NASCUG
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EDACafe.com - What Would Joe Do? - DVCon: You will be Tested

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