Connie O'Dell - DV, EDA, jobseeking, life,whatever: systemC

Showing posts with label systemC. Show all posts

Tuesday, May 28, 2013

SystemC User's Group Meeting June 3 DAC Austin (NASCUG) &c: Accellera at the 50th Design Automation Conference

North American SystemC User's Group Meeting (NASCUG)

Monday, June 3
2:00-6:00 pm
Ballroom D

Pre-registration is required for this free event. Seating is limited, so register today!

A central component of the half-day user's group meeting is a number of short user experience presentations discussing techniques of design, modeling and verification using SystemC.

Agenda available soon on nascug.org.

Join us at DAC events dedicated to technical standards!

Accellera Breakfast and Town Hall Meeting

Topic: "The Standard for Low Power Design and Verification is here! What's next?"

Monday, June 3
7:00-8:45 am
Ballroom D

Moderated by: Ed Sperling, System-level Design

Panelists:

John Biggs, Consultant Engineer, ARM
Sushma Honnavara-Prasad, Sr. Staff Engineer, Broadcom
Qi Wang, Solutions Group Director, Cadence
Erich Marschner, Verification Architect, Mentor Graphics
Jeffrey Lee, Staff Corporate Application Engineer, Synopsys

At our breakfast this year, we will host a town hall discussion about the emerging IEEE 1801-2013 standard. We'll have a panel of experts fresh from the IEEE 1801-2013 tutorial available to answer your questions about this pending standard. With so many of our projects needing power-aware structures, this is sure to be an exciting and informative discussion about the future of low-power design and verification.
Accellera Breakfast Sponsors

North American SystemC User's Group Meeting (NASCUG)

Monday, June 3
2:00-6:00 pm
Ballroom D

Register Here >>>
Pre-registration is required for this free event. Seating is limited, so register today!
A central component of the half-day user's group meeting is a number of short user experience presentations discussing techniques of design, modeling and verification using SystemC.

Agenda available soon on nascug.org.

IP XACT Tutorial: "A Practical Guide to Packaging IP and Assembling SoCs Using the IP-XACT- IEEE1685 Standard"

Monday, June 3
11:00-1:00pm; 2pm-4pm and 5pm-7pm
Location: 14
A practical guide to packaging IP and assembling SoCs using the IP-XACT- IEEE1685 Standard. This all-day DAC tutorial will appeal to those new to the IP-XACT- IEEE1685 standard as well providing additional insight into more advanced IP-XACT topics. The tutorial will be presented by IP-XACT experts and will begin with a brief introduction to IP-XACT, followed by a deeper dive of the core IP packaging and design/assembly metadata concepts of IP-XACT and concludes with an examination of the typical flows that can utilize this metadata. Read more on the DAC website >
Attendees will initially be through typical IP Packaging metadata e.g. components, bus definitions, bus interfaces and HW/SW interface representation. The focus will then move to integration-oriented topics and explore how hierarchical designs are represented and connected. Some advanced integration topics are introduced that explore how system-memory mapping are represented as well as how configurability is addressed. The final section then explores how this component and design metadata can be processed and presents several different example flows.
The presentation technique will focus more on visually presenting the IP-XACT concepts rather than walking through XML snippets.
Organizers:

David Murray / Duolog Technologies Ltd., Galway, Ireland
Kathy Werner / Southwest Reuse, Austin, TX

Speakers:

David Murray / Duolog Technologies Ltd., Galway, Ireland
John Eaton / Ouabache Designworks, Vancouver, WA
Vasant Kumar Easwaran / Texas Instruments India Pvt. Ltd., Bengaluru, India
Mark Noll / Synopsys, Inc., Portland, OR
Kamlesh Kumar Pathak / STMicroelectronics, Greater Noida, India
Sylvain Duvilliard / Magillem Design Services, Cannes, France

DAC Birds-of-a-Feather Meeting:

Topic: "Creating a Standard for Interoperability of Multi-language Verification Environments and Components"
Tuesday, June 4
7:00-9:00pm
Room 11AB
Sign up here >>>
Roughly 18 months ago, the Accellera Board tasked representatives from six electronics companies to define a standard for multi-language verification. Warren Stapleton, chair of the Multi-Language Working Group (MLWG), will review the progress of the group in an open forum. Please join us to learn more about this exciting topic.
The audience for this session is IP stakeholders — the authors, users, and EDA tool vendors. The intent is to provide enough detail for a high-level overview suitable for members of the IEEE 1800 and P1076 working groups and balance that with enough introductory material to explain the concepts to anyone interested.
Accellera Systems Initiative is calling for member participation in the newly formed Multi-Language Working Group.

DAC Birds-of-a-Feather Meeting:

Topic: "Exploring the IEEE P1735-IP Protection Standard"
Tuesday, June 4
7:00-9:00pm
Room 12AB
Sign up here >>>
P1735 has developed recommendations for IP Protection that soon will become a standard. This contains both recommendations and extensions to the IEEE protection pragmas in the SystemVerilog and VHDL LRMs. Its overall goal is to enable IP authors to evaluate and use IP protection to more effectively deliver their IP for use in an interoperable tool flow for a wider IP user community. This session will explain the use models for this protection and how it can work effectively in an interoperable tool flow. It will explain the extensions to support or improve key management, licensing, rights management, and visibility.
Birds of a Feather Meeting Sponsors

Accellera Systems Initiative, 1370 Trancas Street, #163, Napa, CA 94558
Copyright Accellera Systems Initiative. All Rights Reserved. www.accellera.org

Tuesday, February 5, 2013

SystemC Verification: scv-1.0p2-sysc2.2 / src / scv / Makefile.in

Sorry, I know this is not an exciting post, it is just so I can find the info easily later...   :-)


scv-1.0p2-sysc2.2 / src / scv / Makefile.in

# Makefile.in generated by automake 1.6.3 from Makefile.am.
# @configure_input@

# Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
# Free Software Foundation, Inc.
# This Makefile.in is free software; the Free Software Foundation
# gives unlimited permission to copy and/or distribute it,
# with or without modifications, as long as this notice is preserved.

# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
# PARTICULAR PURPOSE.

@SET_MAKE@

srcdir = @srcdir@
top_srcdir = @top_srcdir@
VPATH = @srcdir@
prefix = @prefix@
exec_prefix = @exec_prefix@

bindir = @bindir@
sbindir = @sbindir@
libexecdir = @libexecdir@
datadir = @datadir@
sysconfdir = @sysconfdir@
sharedstatedir = @sharedstatedir@
localstatedir = @localstatedir@
libdir = @libdir@
infodir = @infodir@
mandir = @mandir@
includedir = @includedir@
oldincludedir = /usr/include
pkgdatadir = $(datadir)/@PACKAGE@
pkglibdir = $(libdir)/@PACKAGE@
pkgincludedir = $(includedir)/@PACKAGE@
top_builddir = ../..

ACLOCAL = @ACLOCAL@
AUTOCONF = @AUTOCONF@
AUTOMAKE = @AUTOMAKE@
AUTOHEADER = @AUTOHEADER@

am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
INSTALL = @INSTALL@
INSTALL_PROGRAM = @INSTALL_PROGRAM@
INSTALL_DATA = @INSTALL_DATA@
install_sh_DATA = $(install_sh) -c -m 644
install_sh_PROGRAM = $(install_sh) -c
install_sh_SCRIPT = $(install_sh) -c
INSTALL_SCRIPT = @INSTALL_SCRIPT@
INSTALL_HEADER = $(INSTALL_DATA)
transform = @program_transform_name@
NORMAL_INSTALL = :
PRE_INSTALL = :
POST_INSTALL = :
NORMAL_UNINSTALL = :
PRE_UNINSTALL = :
POST_UNINSTALL = :
build_alias = @build_alias@
build_triplet = @build@
host_alias = @host_alias@
host_triplet = @host@
target_alias = @target_alias@
target_triplet = @target@

EXEEXT = @EXEEXT@
OBJEXT = @OBJEXT@
PATH_SEPARATOR = @PATH_SEPARATOR@

SHELL = /bin/sh
AMTAR = @AMTAR@
AWK = @AWK@
CC = @CC@
CFLAGS_DEBUG = @CFLAGS_DEBUG@
CFLAGS_OPT = @CFLAGS_OPT@
CXX = @CXX@
CXXFLAGS_DEBUG = @CXXFLAGS_DEBUG@
CXXFLAGS_OPT = @CXXFLAGS_OPT@
DBGFLAGS = @DBGFLAGS@
DEPDIR = @DEPDIR@
EXPORT_DYNAMIC = @EXPORT_DYNAMIC@
INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
KIT = @KIT@
LIBIBERTY = @LIBIBERTY@
MAJ = @MAJ@
MIN = @MIN@
OPTFLAGS = @OPTFLAGS@
PACKAGE = @PACKAGE@
RANLIB = @RANLIB@
SHLIB_EXT = @SHLIB_EXT@
STRIP = @STRIP@
SYSC_INC_PREFIX = @SYSC_INC_PREFIX@
SYSC_LIB_PREFIX = @SYSC_LIB_PREFIX@
SYSC_SRC_PREFIX = @SYSC_SRC_PREFIX@
UNDEF_SYMBOLS = @UNDEF_SYMBOLS@
VERSION = @VERSION@
actual_install = @actual_install@
am__include = @am__include@
am__quote = @am__quote@
buildBin = @buildBin@
buildData = @buildData@
buildInc = @buildInc@
buildLib = @buildLib@
cxxDepFlags = @cxxDepFlags@
dummy_install = @dummy_install@
extraExamples = @extraExamples@
install_sh = @install_sh@
overwrite_files = @overwrite_files@
pdfDocSrcDir = @pdfDocSrcDir@
pure_ld_opts = @pure_ld_opts@
purecache = @purecache@
relocate = @relocate@
scvLinkerOpts = @scvLinkerOpts@
AUTOMAKE_OPTIONS = foreign
lib_LIBRARIES = libscv.a

libscv_cxx_files = \
 scv_constraint.cpp \
 scv_constraint_range.cpp \
 scv_debug.cpp \
 scv_expression.cpp \
 scv_init_seed.cpp \
 scv_introspection.cpp \
 scv_random.cpp \
 scv_report.cpp \
 scv_tr.cpp \
 scv_tr_text.cpp \
 scv_util.cpp


libscv_a_SOURCES = ${libscv_cxx_files}
EXTRA_DIST = Makefile.extra $(my_includes) 

my_includes = ${my_scv_includes}

# my_includes = ${my_scv_includes}
my_scv_includes = \
_scv_associative_array.h \
_scv_ext_callbacks.h \
_scv_data_structure.h \
_scv_ext_comp.h \
_scv_ext_rw.h \
_scv_ext_type.h \
_scv_ext_util.h \
_scv_ext_rand.h \
_scv_introspection.h \
_scv_list_iter.h \
_scv_randomization.h \
_scv_smart_ptr.h \
scv_bag.h \
scv_constraint.h \
scv_constraint_range.h \
scv_debug.h \
scv_expression.h \
scv_introspection.h \
scv_messages.h \
scv_object_if.h \
scv_random.h \
scv_report.h \
scv_shared_ptr.h \
scv_sparse_array.h \
scv_tr.h \
scv_util.h \
scv_kit_date.h


INCLUDES = \
 -I${buildInc} \
 -I${top_srcdir}/src \
 -I${top_srcdir}/src/cudd/2.3.0/cudd \
 -I${top_srcdir}/src/cudd/2.3.0/obj \
 -I${top_srcdir}/src/cudd/2.3.0/util \
 -I${top_srcdir}/src/cudd/2.3.0/mtr \
 -I${top_srcdir}/src/cudd/2.3.0/st \
 -I${SYSC_INC_PREFIX} \
 -DSCV_VERSION=\"$(VERSION)\"


BDD_LIBS = \
 ${buildLib}/libobj.a \
 ${buildLib}/libcudd.a \
 ${buildLib}/libutil.a \
 ${buildLib}/libmtr.a \
 ${buildLib}/libst.a


copyFiles = ${top_builddir}/scripts/copyFiles.sh

OBJFILES = ${addsuffix .o, ${basename ${libscv_a_SOURCES}}}

SYSC_LIBRARY = ${SYSC_LIB_PREFIX}/libsystemc.a
subdir = src/scv
mkinstalldirs = $(SHELL) $(top_srcdir)/mkinstalldirs
CONFIG_HEADER = $(top_builddir)/config.h
CONFIG_CLEAN_FILES =
LIBRARIES = $(lib_LIBRARIES)

libscv_a_AR = $(AR) cru
libscv_a_LIBADD =
am__objects_1 = scv_constraint.$(OBJEXT) scv_constraint_range.$(OBJEXT) \
 scv_debug.$(OBJEXT) scv_expression.$(OBJEXT) \
 scv_init_seed.$(OBJEXT) scv_introspection.$(OBJEXT) \
 scv_random.$(OBJEXT) scv_report.$(OBJEXT) scv_tr.$(OBJEXT) \
 scv_tr_text.$(OBJEXT) scv_util.$(OBJEXT)
am_libscv_a_OBJECTS = $(am__objects_1)
libscv_a_OBJECTS = $(am_libscv_a_OBJECTS)

DEFS = @DEFS@
DEFAULT_INCLUDES =  -I. -I$(srcdir) -I$(top_builddir)
CPPFLAGS = @CPPFLAGS@
LDFLAGS = @LDFLAGS@
LIBS = @LIBS@
depcomp = $(SHELL) $(top_srcdir)/depcomp
am__depfiles_maybe = depfiles
@AMDEP_TRUE@DEP_FILES = ./$(DEPDIR)/scv_constraint.Po \
@AMDEP_TRUE@ ./$(DEPDIR)/scv_constraint_range.Po \
@AMDEP_TRUE@ ./$(DEPDIR)/scv_debug.Po \
@AMDEP_TRUE@ ./$(DEPDIR)/scv_expression.Po \
@AMDEP_TRUE@ ./$(DEPDIR)/scv_init_seed.Po \
@AMDEP_TRUE@ ./$(DEPDIR)/scv_introspection.Po \
@AMDEP_TRUE@ ./$(DEPDIR)/scv_random.Po ./$(DEPDIR)/scv_report.Po \
@AMDEP_TRUE@ ./$(DEPDIR)/scv_tr.Po ./$(DEPDIR)/scv_tr_text.Po \
@AMDEP_TRUE@ ./$(DEPDIR)/scv_util.Po
CXXCOMPILE = $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) \
 $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS)
CXXLD = $(CXX)
CXXLINK = $(CXXLD) $(AM_CXXFLAGS) $(CXXFLAGS) $(AM_LDFLAGS) $(LDFLAGS) \
 -o $@
CXXFLAGS = @CXXFLAGS@
DIST_SOURCES = $(libscv_a_SOURCES)
DIST_COMMON = Makefile.am Makefile.in
SOURCES = $(libscv_a_SOURCES)

all: all-am

.SUFFIXES:
.SUFFIXES: .cpp .o .obj
$(srcdir)/Makefile.in:  Makefile.am $(top_srcdir)/src/scv/Makefile.extra $(top_srcdir)/configure.in $(ACLOCAL_M4)
 cd $(top_srcdir) && \
   $(AUTOMAKE) --foreign  src/scv/Makefile
Makefile:  $(srcdir)/Makefile.in  $(top_builddir)/config.status
 cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)

AR = ar
libLIBRARIES_INSTALL = $(INSTALL_DATA)
install-libLIBRARIES: $(lib_LIBRARIES)
 @$(NORMAL_INSTALL)
 $(mkinstalldirs) $(DESTDIR)$(libdir)
 @list='$(lib_LIBRARIES)'; for p in $$list; do \
   if test -f $$p; then \
     f="`echo $$p | sed -e 's|^.*/||'`"; \
     echo " $(libLIBRARIES_INSTALL) $$p $(DESTDIR)$(libdir)/$$f"; \
     $(libLIBRARIES_INSTALL) $$p $(DESTDIR)$(libdir)/$$f; \
   else :; fi; \
 done
 @$(POST_INSTALL)
 @list='$(lib_LIBRARIES)'; for p in $$list; do \
   if test -f $$p; then \
     p="`echo $$p | sed -e 's|^.*/||'`"; \
     echo " $(RANLIB) $(DESTDIR)$(libdir)/$$p"; \
     $(RANLIB) $(DESTDIR)$(libdir)/$$p; \
   else :; fi; \
 done

uninstall-libLIBRARIES:
 @$(NORMAL_UNINSTALL)
 @list='$(lib_LIBRARIES)'; for p in $$list; do \
   p="`echo $$p | sed -e 's|^.*/||'`"; \
   echo " rm -f $(DESTDIR)$(libdir)/$$p"; \
   rm -f $(DESTDIR)$(libdir)/$$p; \
 done

clean-libLIBRARIES:
 -test -z "$(lib_LIBRARIES)" || rm -f $(lib_LIBRARIES)
libscv.a: $(libscv_a_OBJECTS) $(libscv_a_DEPENDENCIES) 
 -rm -f libscv.a
 $(libscv_a_AR) libscv.a $(libscv_a_OBJECTS) $(libscv_a_LIBADD)
 $(RANLIB) libscv.a

mostlyclean-compile:
 -rm -f *.$(OBJEXT) core *.core

distclean-compile:
 -rm -f *.tab.c

@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/scv_constraint.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/scv_constraint_range.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/scv_debug.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/scv_expression.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/scv_init_seed.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/scv_introspection.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/scv_random.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/scv_report.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/scv_tr.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/scv_tr_text.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/scv_util.Po@am__quote@

distclean-depend:
 -rm -rf ./$(DEPDIR)

.cpp.o:
@AMDEP_TRUE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
@AMDEP_TRUE@ depfile='$(DEPDIR)/$*.Po' tmpdepfile='$(DEPDIR)/$*.TPo' @AMDEPBACKSLASH@
@AMDEP_TRUE@ $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
 $(CXXCOMPILE) -c -o $@ `test -f '$<' || echo '$(srcdir)/'`$<

.cpp.obj:
@AMDEP_TRUE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
@AMDEP_TRUE@ depfile='$(DEPDIR)/$*.Po' tmpdepfile='$(DEPDIR)/$*.TPo' @AMDEPBACKSLASH@
@AMDEP_TRUE@ $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
 $(CXXCOMPILE) -c -o $@ `cygpath -w $<`
CXXDEPMODE = @CXXDEPMODE@
uninstall-info-am:

ETAGS = etags
ETAGSFLAGS =

tags: TAGS

ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
 list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
 unique=`for i in $$list; do \
     if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
   done | \
   $(AWK) '    { files[$$0] = 1; } \
        END { for (i in files) print i; }'`; \
 mkid -fID $$unique

TAGS:  $(HEADERS) $(SOURCES)  $(TAGS_DEPENDENCIES) \
  $(TAGS_FILES) $(LISP)
 tags=; \
 here=`pwd`; \
 list='$(SOURCES) $(HEADERS)  $(LISP) $(TAGS_FILES)'; \
 unique=`for i in $$list; do \
     if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
   done | \
   $(AWK) '    { files[$$0] = 1; } \
        END { for (i in files) print i; }'`; \
 test -z "$(ETAGS_ARGS)$$tags$$unique" \
   || $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
      $$tags $$unique

GTAGS:
 here=`$(am__cd) $(top_builddir) && pwd` \
   && cd $(top_srcdir) \
   && gtags -i $(GTAGS_ARGS) $$here

distclean-tags:
 -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH
DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)

top_distdir = ../..
distdir = $(top_distdir)/$(PACKAGE)-$(VERSION)

distdir: $(DISTFILES)
 @list='$(DISTFILES)'; for file in $$list; do \
   if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
   dir=`echo "$$file" | sed -e 's,/[^/]*$$,,'`; \
   if test "$$dir" != "$$file" && test "$$dir" != "."; then \
     dir="/$$dir"; \
     $(mkinstalldirs) "$(distdir)$$dir"; \
   else \
     dir=''; \
   fi; \
   if test -d $$d/$$file; then \
     if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
       cp -pR $(srcdir)/$$file $(distdir)$$dir || exit 1; \
     fi; \
     cp -pR $$d/$$file $(distdir)$$dir || exit 1; \
   else \
     test -f $(distdir)/$$file \
     || cp -p $$d/$$file $(distdir)/$$file \
     || exit 1; \
   fi; \
 done
check-am: all-am
check: check-am
all-am: Makefile $(LIBRARIES)

installdirs:
 $(mkinstalldirs) $(DESTDIR)$(libdir)
install-exec: install-exec-am
install-data: install-data-am

install-am: all-am
 @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am

installcheck: installcheck-am
install-strip:
 $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
   INSTALL_STRIP_FLAG=-s \
   `test -z '$(STRIP)' || \
     echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
mostlyclean-generic:

clean-generic:

distclean-generic:
 -rm -f Makefile $(CONFIG_CLEAN_FILES)

maintainer-clean-generic:
 @echo "This command is intended for maintainers to use"
 @echo "it deletes files that may require special tools to rebuild."
clean: clean-am

clean-am: clean-generic clean-libLIBRARIES mostlyclean-am

distclean: distclean-am

distclean-am: clean-am distclean-compile distclean-depend \
 distclean-generic distclean-tags

dvi: dvi-am

dvi-am:

info: info-am

info-am:

install-data-am:

install-exec-am: install-libLIBRARIES

install-info: install-info-am

install-man:

installcheck-am:

maintainer-clean: maintainer-clean-am

maintainer-clean-am: distclean-am maintainer-clean-generic

mostlyclean: mostlyclean-am

mostlyclean-am: mostlyclean-compile mostlyclean-generic

uninstall-am: uninstall-info-am uninstall-libLIBRARIES

.PHONY: GTAGS all all-am check check-am clean clean-generic \
 clean-libLIBRARIES distclean distclean-compile distclean-depend \
 distclean-generic distclean-tags distdir dvi dvi-am info \
 info-am install install-am install-data install-data-am \
 install-exec install-exec-am install-info install-info-am \
 install-libLIBRARIES install-man install-strip installcheck \
 installcheck-am installdirs maintainer-clean \
 maintainer-clean-generic mostlyclean mostlyclean-compile \
 mostlyclean-generic tags uninstall uninstall-am \
 uninstall-info-am uninstall-libLIBRARIES


libscv${SHLIB_EXT} : ${OBJFILES} ${BDD_LIBS}
 ${CXX} ${scvLinkerOpts} -o libscv${SHLIB_EXT} \
   $(OBJFILES) ${BDD_LIBS} ${LIBS}

all : all-am libscv${SHLIB_EXT}
 ${copyFiles} -s ${srcdir} ${buildInc}/scv ${my_includes}
 ${copyFiles} -s ${srcdir} . ${my_includes}
 ${copyFiles} -s . ${buildLib} ${lib_LIBRARIES} libscv${SHLIB_EXT}

clean-worker :
 -rm -rf libscv${SHLIB_EXT}
 SRC=`cd ${srcdir};pwd`; BLD=`pwd`; \
 if test "$$SRC" != "$$BLD"; then rm -rf ${my_includes}; fi

clean : clean-am clean-worker

distclean : distclean-am clean-worker

install : libscv${SHLIB_EXT}
 ${copyFiles} . ${includedir}/scv ${my_includes}
 ${copyFiles} . ${libdir} libscv${SHLIB_EXT}

uninstall : uninstall-am
 -rm -rf ${libdir}/libscv${SHLIB_EXT}
# Tell versions [3.59,3.63) of GNU make to not export all variables.
# Otherwise a system limit (for SysV at least) may be exceeded.
.NOEXPORT:

https://raw.github.com/systemc/scv-1.0p2-sysc2.2/master/src/scv/Makefile.in

'via Blog this'

Wednesday, January 16, 2013

DVCon 2013: Conference Program is LIVE!

If you're having trouble viewing this email, you may see it online.

Monday, January 14, 2013

Free SystemC/UVM training for beginners, other Doulos free resources

FREE technical resources and webinars

The KnowHow area of the Doulos website contains an extensive catalog of FREE on-line technical resources.You will find up-to-date articles, papers, presentations and plenty of other useful resources in a variety of media, whatever your field of expertise. Here are some examples:

	Doulos Video Gallery Check out the Doulos Video Gallery for a range of useful video resources covering VHDL, SystemVerilog, Verification Methodologies, SystemC, TLM-2.0 and ARM. View the Doulos Video Gallery now
A Designers Guide to Verilog	The basics of Verilog from a hardware designer's perspective. View the Doulos Designer's Guide to Verilog now
	For a complete beginners guide to using SystemC, download the DoulosSystemC Headstart kit
	Easier UVM - Now or Never? FREE on-demand webinar Why you should (or in a few cases should not) be adopting UVM right now: View this webinar now
	ARM Cortex-A9 FREE on-demand webinar Doulos ARM guru, Dr David Cabanis introduces the core architecture of the ARM Cortex-A9 MPCore processor. View it now
	Embedded Software Resources Download real time embedded software related white papers by industry expert Niall Cooling. View the Embedded Software Resources now

Free SystemC training for beginners

'via Blog this'

Wednesday, October 3, 2012

This Friday - Free on-line training - SystemVerilog/VHDL/SystemC

Webinar:
Start date:
Duration:
Presenter:
Summary:

VHDL vs SystemVerilog vs SystemC »
October 5, 2012
x1 1 hour session (all time zones covered)
John Aynsley, Doulos CTO
This webinar will give you an insight into how each of these languages are being used and their relative strengths and weaknesses.

November 2012

Webinar:
Start date:
Duration:
Presenter:
Summary:

Synthesis-Friendly SystemVerilog »
November 2, 2012
x1 1 hour session (all time zones covered)
John Aynsley, Doulos CTO
This webinar will explore the features of SystemVerilog that are useful for RTL synthesis, showing how the RTL SystemVerilog language constructs have been optimized for productivity and reliability.

Future on-line training events

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Advanced VHDL Verification: OSVVM »
TBC
x1 1 hour session (all time zones covered)
Alan Fitch, Principal Member Technical Staff
This webinar will introduce you to Open Source VHDL Verification Methodology (OSVVM): what it does, how to use it, and how it compares with UVM.

Doulos Webinars

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Monday, September 10, 2012

High-Level Synthesis not just for Hardware Design, It’s for Verification Engineers, too! - Brett Cline

CynCity

Brett Cline
Brett Cline is vice president of marketing and sales at Forte Design Systems. Before joining Forte in 1999, he was Director of Marketing at Summit Design, where he managed both the verification product line, including HDL Score, and marketing communications. Cline joined Summit through the … More »

High-Level Synthesis is not just for Hardware Designers, It’s for Verification Engineers, too!

September 6th, 2012 by Brett Cline

We’ve seen an uptick in interest in high-level synthesis (HLS) around the world lately. Some of the increased interest is from designers that have MBOs to investigate HLS in 2012. Some interest is from the visibility that Forte’s Cynthesizer and HLS have had this year. And some is from people that simply do not have enough time to get their projects done with the allocated resources. This is where we can really help.
Cynthesizer automates many of the mundane coding tasks that hardware designers have to suffer with using Verilog daily. Through that automation, it will allow designers to quickly perform “what if analysis” on their macro and micro-architectural decisions without wasting months of effort.

Since the design model will now be in SystemC, a C++ class library, the functional code will be written in C or C++. Technically, it’s all C++ because we are using a C++ compiler, but the reality is that ANSI-C can pretty much be used as-is. The benefit of SystemC and C++ come from the addition of hierarchy, clock and bit accuracy, and other hardware specifics not available in standard ANSI-C. And, since SystemC is an IEEE standard, designers know that they are being locked into a proprietary language or set of extensions.
We are often asked about the verification benefits of using SystemC models for design and it’s a great question. While there are numerous others, here are three areas that will benefit from the higher-level approach.
First, hardware design and verification teams will benefit from significantly higher performance models. SystemC models typically run between 10x and 100x faster than RTL Verilog and even faster in some cases. This allows verification teams to setup and debug their verification environment faster, as well as run far more cycles through the high-level model. Since the model can be either a transaction-level model (TLM) or a pin-cycle accurate model (PCA), the verification team can vary the level of interface detail while maintaining high-level functional code.
Second, this model can be used for Virtual System Prototypes (VSPs). These highly abstracted models require far less code to implement (usually 10-20x less code) and are available months before the RTL designs.
Third, the SystemC model with HLS can be quickly targeted for an acceleration or emulation platform, including some of the big emulator “boxes” as well has home-grown FPGA solutions. This flow gives design and verification teams the best of both worlds –– the ability to quickly make changes, and get results into the hardware and get hardware accurate simulations at high speeds. Since SystemC models for Cynthesizer are technology independent, they can be quickly retargeted from FPGA to ASIC and back saving time.
Obviously, some of these benefits are hard to quantify. If we simply look at hardware verification benefits, we can quantify some. Working with a design team, we collected data using an ARM bus-based multi-function printer system. The design consisted of several blocks, both control and datapath, entirely in SystemC.
Here’s a look at simulation performance and the huge difference between the TLM behavioral model and the Verilog RTL model –– almost 500x!:

Simulation	Runtime(hh:mm:ss)	Ratio (Compared to TLM)
TLM Behavior	00:00:11	1
PIN Behavior	00:04:40	25
Verilog RTL	01:28:21	482
Cycle-Accurate RTL*	00:25:51	141

* This is a process by which the Cynthesizer RTL output is converted to cycle accurate SystemC and simulated in SystemC.
We also measured lines of code for each design:

SystemC TLM	3511
Generated RTL code	59812 (17x)

While generated code tends to be a bit more verbose than handwritten Verilog RTL code, it’s not off by much and it’s easy to see a 10x reduction here. In a paper published at DVCon 2012, a Cynthesizer user claimed a nearly 40x reduction in code. Now that is productivity improvement!
SystemC and HLS provide a myriad of benefits to the designers in the form of better productivity, better quality of results (QoR), and true design reuse through technology-independent design. What had been less clear are the substantial benefits in verification as well.
From high-level models developed much faster to high-speed verification, high-level synthesis really is about delivering a better methodology. It allows designers and verification engineers to spend time on real hardware design problems, not on mundane tasks required by the 20+ year old Verilog RTL methodology.

This entry was posted on Thursday, September 6th, 2012 at 8:36 am. You can follow any responses to this entry through theRSS 2.0 feed. You can leave a response, or trackback from your own site.

EDACafe.com - CynCity - High-Level Synthesis is not just for Hardware Designers, It’s for Verification Engineers, too!

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Wednesday, September 5, 2012

"Update on SystemC Synthesis and Training", [Forte Design Systems]

"Update on SystemC Synthesis and Training", Sean Dart
Forte Design Systems

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Thursday, August 23, 2012

What does C++11 mean for SystemC?

Training Schedule & KnowHow Update

North America: Scheduled Courses

Embedded Systems and ARM

ESL and SystemC

Hardware Design

SystemVerilog and UVM

Paper and code download: What does C++11 mean for SystemC?

In September of 2011, ISO approved an update to the C++ standard, which is known variously as ISO/IEC 14882:2011, C++0x and C++11. This paper by Senior Member of Technical Staff, David C Black, takes a quick look at some of the features and illustrates how they can change the way we write SystemC code for the better.

View "What does C++ mean for SystemC?" now

The Doulos Guide
to SystemC

Extended video with download: First Steps with UVM - Part 2

Doulos CTO, John Aynsley, presents a simple, complete SystemVerilog UVM source code example (which you can download), explaining what is happening and highlighting best practice. You are shown how to drive pins on the design-under-test interface from the UVM verification environment, and how to pass a virtual interface using the configuration database.

More info: UVM - The Universal Verification Methodology

FREE KnowHow: Latest updates in Doulos KnowHow

First Steps with UVM: Part 2

Missed Part 1? Click here