SystemC User's Group Meeting June 3 DAC Austin (NASCUG) &c: Accellera at the 50th Design Automation Conference

North American SystemC User's Group Meeting (NASCUG)

Monday, June 3
2:00-6:00 pm
Ballroom D

Register Here >>> 

Pre-registration is required for this free event. Seating is limited, so register today!

A central component of the half-day user's group meeting is a number of short user experience presentations discussing techniques of design, modeling and verification using SystemC.

Agenda available soon on nascug.org.

Join us at DAC events dedicated to technical standards!

 

Accellera Breakfast and Town Hall Meeting

Topic: "The Standard for Low Power Design and Verification is here! What's next?"

Monday, June 3
7:00-8:45 am
Ballroom D

Register Here >>>
Pre-registration is required for this free event. Seating is limited, so register today!

Moderated by: Ed Sperling, System-level Design

Panelists:

• John Biggs, Consultant Engineer, ARM
• Sushma Honnavara-Prasad, Sr. Staff Engineer, Broadcom
• Qi Wang, Solutions Group Director, Cadence
• Erich Marschner, Verification Architect, Mentor Graphics
• Jeffrey Lee, Staff Corporate Application Engineer, Synopsys

At our breakfast this year, we will host a town hall discussion about the emerging IEEE 1801-2013 standard. We'll have a panel of experts fresh from the IEEE 1801-2013 tutorial available to answer your questions about this pending standard. With so many of our projects needing power-aware structures, this is sure to be an exciting and informative discussion about the future of low-power design and verification.

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North American SystemC User's Group Meeting (NASCUG)

Monday, June 3
2:00-6:00 pm
Ballroom D

Register Here >>> 
Pre-registration is required for this free event. Seating is limited, so register today!
A central component of the half-day user's group meeting is a number of short user experience presentations discussing techniques of design, modeling and verification using SystemC.

Agenda available soon on nascug.org.

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IP XACT Tutorial: "A Practical Guide to Packaging IP and Assembling SoCs Using the IP-XACT- IEEE1685 Standard"

Monday, June 3
11:00-1:00pm; 2pm-4pm and 5pm-7pm
Location: 14
A practical guide to packaging IP and assembling SoCs using the IP-XACT- IEEE1685 Standard. This all-day DAC tutorial will appeal to those new to the IP-XACT- IEEE1685 standard as well providing additional insight into more advanced IP-XACT topics. The tutorial will be presented by IP-XACT experts and will begin with a brief introduction to IP-XACT, followed by a deeper dive of the core IP packaging and design/assembly metadata concepts of IP-XACT and concludes with an examination of the typical flows that can utilize this metadata. Read more on the DAC website >
Attendees will initially be through typical IP Packaging metadata e.g. components, bus definitions, bus interfaces and HW/SW interface representation. The focus will then move to integration-oriented topics and explore how hierarchical designs are represented and connected. Some advanced integration topics are introduced that explore how system-memory mapping are represented as well as how configurability is addressed. The final section then explores how this component and design metadata can be processed and presents several different example flows.
The presentation technique will focus more on visually presenting the IP-XACT concepts rather than walking through XML snippets.
Organizers:

• David Murray / Duolog Technologies Ltd., Galway, Ireland
• Kathy Werner / Southwest Reuse, Austin, TX

Speakers:

• David Murray / Duolog Technologies Ltd., Galway, Ireland
• John Eaton / Ouabache Designworks, Vancouver, WA
• Vasant Kumar Easwaran / Texas Instruments India Pvt. Ltd., Bengaluru, India
• Mark Noll / Synopsys, Inc., Portland, OR
• Kamlesh Kumar Pathak / STMicroelectronics, Greater Noida, India
• Sylvain Duvilliard / Magillem Design Services, Cannes, France

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DAC Birds-of-a-Feather Meeting:

Topic: "Creating a Standard for Interoperability of Multi-language Verification Environments and Components"
Tuesday, June 4
7:00-9:00pm
Room 11AB
Sign up here >>>
Roughly 18 months ago, the Accellera Board tasked representatives from six electronics companies to define a standard for multi-language verification. Warren Stapleton, chair of the Multi-Language Working Group (MLWG), will review the progress of the group in an open forum. Please join us to learn more about this exciting topic.
The audience for this session is IP stakeholders — the authors, users, and EDA tool vendors. The intent is to provide enough detail for a high-level overview suitable for members of the IEEE 1800 and P1076 working groups and balance that with enough introductory material to explain the concepts to anyone interested.
Accellera Systems Initiative is calling for member participation in the newly formed Multi-Language Working Group.

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DAC Birds-of-a-Feather Meeting:

Topic: "Exploring the IEEE P1735-IP Protection Standard"
Tuesday, June 4
7:00-9:00pm
Room 12AB
Sign up here >>>
P1735 has developed recommendations for IP Protection that soon will become a standard. This contains both recommendations and extensions to the IEEE protection pragmas in the SystemVerilog and VHDL LRMs. Its overall goal is to enable IP authors to evaluate and use IP protection to more effectively deliver their IP for use in an interoperable tool flow for a wider IP user community. This session will explain the use models for this protection and how it can work effectively in an interoperable tool flow. It will explain the extensions to support or improve key management, licensing, rights management, and visibility.

 

Accellera Systems Initiative, 1370 Trancas Street, #163, Napa, CA 94558
Copyright Accellera Systems Initiative. All Rights Reserved. www.accellera.org

Video tutorial: UVM, Ready, Set, Deploy, thanks to Accellera

Home - Accellera Systems Initiative:

http://www.accellera.org/news/videos/uvmreadysetdeploy

New Video Tutorial – UVM: Ready, Set, Deploy!

It’s been six months since Accellera and the Open SystemC Initiative joined forces to become Accellera Systems Initiative. In that time, we have achieved several milestones in developing standards that address the real needs of system and semiconductor designers.

The Universal Verification Methodology (UVM) standard continues to gain adoption across the verification community. Presented by expert verification methodology architects and engineers at DVCon 2012, the eight-part video tutorial is available at no cost to users and provides an introduction to key UVM concepts and best practices.

See us at the Design Automation Conference, June 4-7 in San Francisco! We will be hosting several events at this year's DAC including a luncheon on the Unified Coverage Interoperability Standard (UCIS), NASCUG meeting, and special birds-of-a-feather sessions. At the luncheon, Accellera Systems Initiative will receive the Tenzing Norgay Award, and will present its 2012 Leadership Award. Events are no charge with advance registration required. Read the latest article on UCIS featured in our newsletter.

Dennis Brophy Receives 2012 Accellera Systems Initiative Leadership Award 

To be presented at our luncheon at DAC in San Francisco on Wednesday, June 6, 2012

Details >>>

DAC 2012

June 6 | San Francisco, CA

• Hosted Luncheon and UCIS Technical Presentation
• Birds-of-a-Feather Meetings
• NASCUG XVIII

Find out more >

SystemC Japan

July 6 | Yokohama, Japan

DVCon 2013

Call for abstracts >

Subscribe to our mailing list:

Recent Happenings  • UVM 1.1b Reference Implementation now available • Accellera Systems Initiative receives 2012 Tenzing Norgay Award from Synopsys. See press release > • May newsletter now available. • John Aynsley receives the 2012Technical Excellence Award.    • IEEE 1666-2011 Now Available for Free Download courtesy of Accellera Systems Initiative. • Open Verification Library (OVL) 2.6release is now available for download. OSCI and Accellera Unite The new organization will leverage the complementary efforts of both groups to create more comprehensive standards. • Welcome from the Chair  • Read what Accellera Systems Initiative members and others are saying • Frequently Asked Questions

News Dennis Brophy to Receive Accellera Systems Initiative Leadership Award 30 May 2012 Accellera Systems Initiative Hosts User Events at the 2012 Design Automation Conference 23 May 2012 ISCUG 2012 Slated for April 9-10 in Bangalore 29 Mar 2012 Featured Quote "We continue to work with the IEEE to make approved EDA and IP standards available," said Shishpal Rawat, chair of Accellera Systems Initiative. "Through the IEEE Get Program, we provide valuable standards documentation at no cost to the worldwide electronics industry community to support and foster electronic design innovation."... More » Other News From the Industry Synopsys Honors Accellera Systems Initiative with 2012 Tenzing Norgay Interoperability Achievement Award Open SystemC Initiative and Accellera merger paves way for broad interoperability standards MOUNTAIN VIEW, Calif., May 24, 2012 -- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, announced that Accellera Systems Initiative will receive Synopsys’ twelfth annual Tenzing Norgay Interoperability Achievement Award for advancing industry standards that enable interoperable system design flows. More »

Featured Videos UVM - Ready, Set, Deploy

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DAC 2012 Freebies, Silicon Valley Special Offer

They seem pretty motivated to get your attendance, if you are in Silicon Valley (or if you can swing a stay on somebody's couch there).

It is something I would recommend if you are job-seeking in this field, even if CA is not where you want to be, it is a great place for networking.

Of course, if you want to be in Colorado in hardware design/verification/EDA, (or even better compiler engineering!) you should definitely drop me an email or a LinkedIn connection  :-)

Cheers, 
Connie L. O'Dell 
Sr. Verification Specialist 
c.odell@co-consulting.net 
303-641-5191 
_____________________________________________ 
CO Consulting - Boulder, CO - http://co-consulting.net

---------- Forwarded message ----------
From: EDA Consortium <events12@edac.org>
Date: Tue, May 29, 2012 at 6:35 PM
Subject: DAC 2012 Silicon Valley Special Offer

...

We're eagerly anticipating the 49th Design Automation Conference in San Francisco next week. Many thousands of design professionals, researchers and 'chipheads' will share the very latest at DAC. May we invite you to join the DAC excitement, in nearby San Francisco? There is free bus service from the south bay, making a day at DAC easier than ever.

Next to our full registration, we can offer complementary registration for the User Track, tutorials, keynotes, and exhibition (details here).  That makes spending a day at DAC more convenient than ever. Please pass this around among your colleagues.

For 2012, we have the most exciting and elaborate program in half a century of DAC legacy. A few of the highlights are:

• Keynotes by Mike Muller (ARM's founder & CTO) and the chief architects of Intel's and IBM's hottest chips on design practices
• Chose from hundreds of presentations on the on latest methods and technologies. 
• 100+ presentations by IC designers from leading companies on design practices in the User Track
• Hard-hitting compact tutorials on System C design, Analog Design, lithography challenges in 10nm and 14nm, etc.
• Dynamic panel sessions on future design trends and hypes, cloud, 3D, tear downs and much much more!
• Over 200 companies lined up in the exhibition, officering a complete coverage of commercial design tools and IP solutions.
• Meet colleagues and old friends during the daily cocktail receptions. 
• Much more! check out the program at http://www.dac.com/dac+2012+conference+program.aspx
• Free bus service from the south bay makes the trip up to San Francisco easy and stress free. 

It would be our pleasure to welcome you at DAC, the place we design meets automation! Please check out http://www.dac.com to see  what DAC has to offer and register today. 

We look forward to see you at 49th DAC, at the home of the 49ers!

Regards,

Bob Gardner
Executive Director
EDA Consortium

EDA Consortium | 111 West Saint John St. | Suite 220 | San Jose | CA | 95113

Denali/Cadence DAC Party Still Alive?: (was: Industry Insights Blog)

I do not know what the attendee screening rules are like, of course, but it is nice to see it continuing...

"... Learn about all Cadence DAC activities, including the Denali Party, here  ..."

Industry Insights Blog

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Free DAC Breakfasts: HW/SW Co-Development, 28nm/20nm Challenges Posted: 14 May 2012 06:00 AM PDT Don't go into the frenzied activity of the Design Automation Conference (DAC) without a good breakfast! Fortunately, you can get a good breakfast and learn a lot from two events sponsored by Cadence Tuesday, June 5 and Wednesday, June 6 at the 49th DAC in San Francisco.   Tuesday June 5 Addressing Hardware/Software Co-Development, System Integration, and Time to Market Time: 8:00 AM - 10:00 AM (doors open and breakfast is served at 7:30 AM) Location: 270-276 (Moscone Convention Center) This breakfast will feature speakers from Cadence and LSI Corp. Speakers will present the following topics: Cadence System Development Suite overview "Intelligent instrumentation" using the System Development Suite Improving FPGA bring-up time using the Palladium front end (LSI) Real-world system validation using Palladium XP Verification IP catalog update The breakfast session will conclude with a panel discussion in which Cadence technologists and guests will answer your questions about system-level development challenges. Wednesday June 6 The Path to Yielding at 2(x)nm and Beyond Time: 8:00 AM - 9:00 AM (doors open and breakfast is served at 7:30 AM) Location: 270-276 (Moscone Convention Center) This breakfast will include speakers from Cadence, IBM and Samsung. A panel will look at process and design challenges at advanced nodes and discuss what it takes to ramp up to volume production. The panel will examine challenges from the foundry, EDA and customer perspectives. Interested? Learn more about Cadence DAC lunches and breakfasts here Register for lunches and breakfasts here Learn about all Cadence DAC activities, including the Denali Party, here See you in San Francisco! Richard Goering

Free DAC Lunches: Custom/Analog Variability, ARM Low Power Processors in Mixed-Signal Designs Posted: 14 May 2012 06:00 AM PDT There is such a thing as a free lunch - if you're at the 49th Design Automation Conference (DAC) in San Francisco June 3-7. Cadence is sponsoring two lunches at which you can learn about two important technology topics - custom/analog variability, and the use of ARM processors in low-power, mixed-signal designs.   Monday June 4 Overcoming Variability and Productivity Challenges in Your High-Performance, Advanced Node, Custom/Analog Design Time: 12:00 PM - 1:00 PM (doors open and food is served at 11:30 AM) Location: 270-276 (Moscone Convention Center) Speakers at this lunch include Francois Lemery, CAD Project Manager, STMicroelectronics; Vinod Kariat, Fellow, Cadence; and Thomas Volden, Architect, Cadence. Speakers will show why variability is introducing new challenges at advanced process nodes, including layout-dependent effects. Cadence experts will demonstrate a comprehensive flow that can reduce total design time, manage layout-dependent effects, and optimize circuit performance without over-designing. Tuesday June 5 Overcoming the Challenges of Embedding Ultra Low-Power, ARM 32-bit Processors into Analog/Mixed-Signal Designs Time: 12:00 PM - 1:00 PM (doors open and food is served at 11:30 AM) Location: 270-276 (Moscone Convention Center) Speakers at this luncheon include Rob Cosaro, MCU System and Architecture group, NXP; Keith Clarke, VP Embedded Processors, ARM;  John Murphy, Alliance Group Director, Cadence; Mladen Nizic, Engineering Director, Cadence; and Jamie Davey, ARM Alliance Director, Cadence. Speakers will participate in a roundtable discussion showing how you can integrate ARM Cortex-M processors and other design IP into your mixed-signal design more efficiently. Attendees will learn about the advantages of the new Cortex-M0 processor, ARM Cortex-M based MCUs from NXP, and the Cadence low-power and mixed-signal design solution. Interested? Learn more about Cadence DAC lunches and breakfasts here Register for lunches and breakfasts here Learn about all Cadence DAC activities, including the Denali Party, here See you in San Francisco! Richard Goering

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2012 DAC Roadmap (events) from EDAC!

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Sunday, June 3rd: DAC 2012 Kick-Off Reception. Join industry leaders as we open DAC 2012 with a lively evening of networking, food, and fun, hosted by the DAC Executive Committee and the EDA Consortium. (More information and registration.) Lodging and accommodations for this year's DAC: DAC 2012 will be at the Moscone Center in San Francisco. Hotel and reservations are available on the DAC web site. New for 2012! Stress Free Transportation to DAC (from Silicon Valley) Sunday, June 3rd: Gary Smith's EDA Update. After the EDAC/DAC Kick-Off reception, come hear Gary Smith & Sharon Tan discuss "How to Acheive 44% Design Cost Reduction". This year's talk will focus on multi-platform designs and how these platforms are dramatically cutting the cost of design.More information and video. Monday — Wednesday, June 4th — 6th: Free Exhibits! Once again, EDAC members Atrenta, Cadence, and Springsoft are offering complimentary admission to the exhibit floor (Restrictions apply). (More information and registration.) Monday, June 4th: Pavilion Panel Opening. Gary Smith of Gary Smith EDA reviews EDA's hottest technology trends. How will the dramatic changes in EDA, the semiconductor market and the design community affect you? What are the hot 'must sees' at this year's conference? Find out here, and watch the video!   EDA Consortium helps protect your company against software piracy, export constraints, and proliferation of operating systems. Membership also covers educational and networking opportunities. Additional benefits include timely, detailed market data on EDA, SIP, and services.   Tuesday, June 5th: Phil Kaufman Award Re-Presentation. Join the EDA Consortium and the IEEE Council on EDA prior to Tuesday Morning's Keynote Address at 8:30 AM in Ballroom 102/103, as we proudly honor Dr. C. L. David Liu with the 2011 Phil Kaufman Award. Dr. Liu was selected to receive the award for his work in leading the transformation from ad hoc EDA to algorithmic EDA. (Admission is included with conference and exhibitor registration.) (More information.) Tuesday, June 5th: EDA Heritage Series. Join us in the Pavilion Panel for an interview with 1997 Phil Kaufman award recipient Jim Solomon, as he illuminates the mystic world of analog (More information and video.) Wednesday, June 6th & Thursday, June 7th: EDAC/CELUG Event This interactive event will focus on Enterprise Licensing and EDA/HPC IT, with presentations and panels addressing current and future challenges to making high-technology tools and users more productive. (More information.)

© Copyright 1998-2012 EDA Consortium. All Rights Reserved. EDA Consortium and EDA Where Electronics Begins are trademarks of Electronic Design Automation Consortium.

Nice DVCon explanation from Peggy Aycinena, sorry it's late (there's always next year)

EDACafe.com - What Would Joe Do? - DVCon: You will be Tested

DVCon: You will be Tested

February 10th, 2012 by Peggy Aycinena

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Pay close attention. You will be tested on the following.
DVCon stands for Design & Verification Conference. Not surprisingly, it’s targeted at design and verification engineers. Despite rumors on the street, design and verification engineers are still two different types of employees, particularly at the big design houses. That’s why DVCon is applicable to both. Two disciplines. One conference.
DVCon happens every year around this time at the Double Tree Inn in San Jose. Approximately 700 people attend. The conference is 4 days long, including 2 days of tutorials on either side of 2 days of technical sessions. There’s always one major panel, this year on February 28th, that showcases industry execs. Famously, it used to be moderated by John Cooley. Now it’s moderated by JL Gray, who is also famous.
JL’s panel this year will include Ted Vucurevich, John Costello (sic erat scriptum), Gary Smith, andJim Hogan. If you do not know who these people are, perhaps you should not be coming to DVCon. Unless you’re a design or verification engineer, in which case that’s okay. You’ll probably know someone on the panel the next day hosted by Brian Bailey, who is not famous. He is legendary. Brian’s panel is about Hardware-Assisted Verification and includes people from Qualcomm, ARM,SpringSoft, Xilinx, and Cadence.
DVCon also has a major keynote, this year on February 29th, which features the CEO of one of the Big 3 EDA companies. Last year it was Mentor’s Wally Rhines. This year it’s Synopsys’ Aart de Geus. His talk is entitled: Principles for Success in IC Design. DVCon is well known for this type of positive thinking. Last year, JL Gray’s panel was entitled: Making Great Products Great. This year it’s entitled: The Resurgence of Chip Design. You will not find a keynote at DVCon entitled:Principles for Failure in IC Design, nor a panel entitled: Making Great Products Lousy. That kind of thinking is not what DVCon is all about.
DVCon is sponsored these days by Accellera Systems Initiative, a single organization created last year out of two separate organizations, Accellera and OSCI. That’s because both organizations are interested in system-level design. NASCUG is also interested in system-level design. It too has a presence at DVCon. If you don’t know what NASCUG means, click here. Meanwhile, remember that Accellera was itself created in 2000 out of two separate organizations, OVI and VHDL International. This type of thing is also what DVCon is all about. People helping people make their organizations better. People helping people figure out how we can all get along.
Creating standards is another way of figuring out how we can all get along. Which brings us toKaren Bartleson. Like Accellera Systems Initiative, Bartleson is a single person who represents two complementary ideas: Standards and Positive Thinking. This is why Karen is the perfect person to be General Chair of DVCon. She is Synopsys’ go-to person for all things related to Standards, and she is nothing, if not all about Positive Thinking. Add these together, and multiply by two, and you see why this is the second year in a row that Karen has been DVCon General Chair.
Karen will not be General Chair next year. She will be busy doing something else. She will be serving as President of the IEEE Standards Association, overseeing 900 different standards and the 15,000 people who maintain and update those standards. Maybe she could invite all of those people to DVCon in 2013, although it might get a little crowded if they all came. MP Associates, the folks who run DVCon (and DAC among other things), might run out of conference bags. Nonetheless, MP Associates is a very capable organization. If Karen Bartleson got all 15,000 IEEE standards committee members to come to DVCon next year, I’m sure that MP Associates would be up to the task.
Speaking of people who like people, that brings us to the idea of networking, wine/beer, and exhibit halls. DVCon serves up a generous dollop of all three, along with the tutorials, keynotes, panels, and technical sessions. I have checked with Karen Bartleson and she assures me that when the DVCon 2012 Exhibit Hall is open – February 28th from 3:30 to 6:30 pm, and February 29thfrom 4:00 to 7:00 pm – there will be lots of networking, food, wine/beer, and sanctioned recruiting amidst the 30+ exhibitor booths.
She also emphasized that the wine/beer will be complementary to all attendees. That might be a tall order for next year if 15,000 people come to DVCon. All the more reason why you should beplanning to come this year. Serving up wine and hors d’oeuvres to 700 people is an order of magnitude easier than serving same to 15,000. Even if highly capable MP Associates could pull it off. Or if DVCon organizers could afford it.
Speaking of money, DVCon is good there as well. They have made enough money to be profitableseveral years in a row. Accellera Systems Initiative, apparently, also has some extra money because they will be presenting a monetary award to the Best Paper winners at DVCon. Yet another reason to attend. The Best Paper selection will be done by the attendees themselves, voting throughout the conference to determine who will be announced Big Winner in the last session on February 29th. Karen said receiving Best Paper at DVCon is something special, particularly given the quality of the papers submitted.
Okay, if you’ve read carefully to this point, there’s only three things left to do.
* Register for DVCon.
* Watch Karen Bartleson’s upcoming Conversation Central interview with the DVCon 2012Technical Program Chair and Tutorials & Panel Chair on February 16th.
* Take the quiz, which will be posted here on February 17th.
*************************

Tags: Aart de Geus, Accellera Systems Initiative, Brian Bailey, DVCon, JL Gray, Karen Bartleson,NASCUG
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EDACafe.com - What Would Joe Do? - DVCon: You will be Tested

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Verification presentations, courtesy of DVClub

Some very interesting material, speakers commonly post slides for your edification, very useful newsletter.

Cheers,
Connie L. O'Dell
Sr. Verification Specialist
c.odell@co-consulting.net
303-641-5191
_____________________________________________
CO Consulting - Boulder, CO - http://co-consulting.net

---------- Forwarded message ----------
From: DVClub Newsletter <admin@dvclub.org>
Date: Thu, Nov 10, 2011 at 5:38 PM
Subject: DVClub Newsletter: November 2011

Is this email not displaying correctly? View it in your browser. In this Issue: DVClub Events DVClub Austin held jointly with MTVCon: Dec 7 DVClub News DVClub in the Blogosphere Software-Inspired Technique Predicts IC Verification Closure RAM-Resident Database Speeds Verification Coverage Collection Get Involved: Industry Events Attend MTVCon in Austin Dec 5-7 DAC 2012 - Key Deadlines Sponsor News/Events MTVCon Scholarship - Deadline Extended [ARM] CDNLive! - Call for Papers [Cadence] DVClub Events Austin - December 7 - Cool River Cafe - Register The Cortex-A15 Verification Story Learn the details of verifying the Cortex-A15 MPCore: this processor has an out-of-order superscalar pipeline with a tightly-coupled low-latency level-2 cache which can be up to 4MB in size. It can be configured in clusters with up to 4 cores, and supports MP cache coherency in hardware. Additional improvements in floating point and NEON™ media performance result in devices that deliver the next-generation user experience for consumers as well as high-performance computation for web infrastructure applications. This processor introduces new technology that enables efficient handling of complex software environments including full hardware virtualization, Large Physical Address Extensions (LPAE) addressing up to 1TB of memory as well as error correction capability for fault-tolerance and soft-fault recovery. This presentation will describe the advanced verification methodologies which are employed in the verification of Cortex-A15, including: Constrained random SystemVerilog unit level testbenches Coverage driven methodology utilizing black box and white box functional coverage for each unit Assertion based design where assertions are added by both verification engineers as well as RTL designers Top level (full CPU cluster) verification with multiple diverse random instruction generators, focusing on comprehensive ISA coverage and extensive stress of MP cache coherency System level (multiple CPU clusters + interconnect, memory controllers, graphics accelerators, other peripherals) emulation of the platform to enable booting of operating systems and running stress testing applications and workloads FPGA platforms to provide additional cost effective throughput Bill Greene, Austin CPU Validation Manager, ARM, is the engineering manager for the CPU Validation Team at ARM in Austin. He previously worked at Intel on Itanium processor validation and firmware development, and as RTL and verification manager at Marvell developing ARM-based SoCs for mobile applications. He holds BSEE/BSCE and MSEE degrees from Purdue University. Micah McDaniel, Principal Design Engineer, ARM, was the verification lead for the Cortex-A15 processor. At ARM he was previously an RTL designer and verification engineer on Cortex-A8. He has also done RTL design at Chicory Systems, and circuit design at IBM. He holds an MSEE from the University of Texas, and BSEE/BSCE and BSPHYS from Louisiana State University. Register Now! DVClub News Recent DVClub Event Updates Hands-On Verification - Doug Smith, Engineer/Instructor, Doulos Austin, August 15th New Reference Link posted in lieu of slides Additional Bonus: FREE WEBINAR: Easier UVM Training Using Bug Arrival Rates to Predict the Future - Greg Smith, Sr. Verification Manager, Oracle Silicon Valley, August 17th Slides Posted High Performance Collection of Coverage Metrics Using a Relational Database Backend - James Roberts, Sr. Verification Engineer, Oracle Silicon Valley, August 17th Slides Posted DVClub in the Blogosphere - with special thanks to blogger Richard Goering DVClub Talk: Software-Inspired Technique Predicts IC Verification Closure What's the hardest question for a verification manager to answer? Greg Smith, senior verification manager at Oracle, found that out soon after he moved from design into verification at Hewlett-Packard some years ago. The question is, "when will you be done?" DVClub Talk #2: RAM-Resident Database Speeds Verification Coverage Collection Metric-driven verification provides a great deal of valuable coverage data, but where are you going to store it all? Merging coverage data from hundreds or thousands of parallel simulation runs can pose a huge bottleneck. One way to avoid that bottleneck is to write to a memory-resident relational database, according to James Roberts, a verification engineer at Oracle who works with Sparc processors. Industry Events DAC 2012 Deadlines Have an emerging topic that's timely, enlightenting, and relevant to various segments of the Design and Automation community? Call for Contributions MTVCon 2011 12th Annual Microprocessor Test and Verification International Workshop Join Leading Researchers & Practitioners in the Verification & Test Community Austin, Texas - Hyatt Regency - December 5-7 Join attendees from industry and academia, including strong representation from companies such as AMD, Apple, ARM, Cadence, Freescale, IBM, Intel, Mentor Graphics, Oracle and Synopsys, among others. This year's theme is Common Challenges and Solutions. Network with peers and luminaries. Exchange innovative ideas. Tackle difficult challenges in various processor and SOC design environments. Design Verification Alerts from DVClub Sponsors ARM Offers Scholarship for MTVCon - Deadline Extended! ARM is offering numerous educational scholarships to the 12th Annual International Workshop on Microprocessor Test and Verification (MTVCon), to be held December 5-7, 2011 in Austin, TX. Eligibility is limited to graduate students and graduates new to the verification field. Deadline now extended. For more info, visit: ARM 2011 MTVCon Scholarship Know a grad student or a new grad who would be perfect for this? Forward to a Friend! Cadence CDNLive! Silicon Valley - Calls for Papers Abstracts are due before 5pm PST, on Friday, November 11, 2011 March 13-14th, 2012 - San Jose, CA | follow on Twitter | forward to a friend If you need assistance, please contact us at admin@dvclub.org Design Verification Club 1250 S. Capitol of Texas Hwy Building 1, Suite 520 Austin, TX 78746 Copyright © 2011 Design Verification Club, All rights reserved.

Design Verification Club · 1250 S. Capitol of Texas Hwy · Building 1, Suite 520 · Austin, TX 78746

10 ways to get your EDA tools to run faster, smoother, and longer , courtesy of Steve Leibson

10 ways to get your EDA tools to run faster, smoother, and longer | EDA360 Insider:

The IT troubleshooter drops his pack into a chair across the table from me and sits down. “We take care of…problems” he says. The problems he’s referring to are sluggish EDA tools. Perhaps you’ve encountered a few. Perhaps you suspected the performance problems were the fault of the tools. Sometimes, it is but more often, it’s not. It’s the infrastructure running the tools. Peter Vincent’s mission is to debug IT infrastructures that inhibit EDA tool performance and he has some free tips for you if you need help in this department.

Vincent says that the three biggest problems are:

1. Linux – Especially software revisions and configuration problems
2. Storage – Not all storage performs equally well and EDA hammers storage hard enough to surface any weaknesses in storage subsystems
3. Network – Typically the “elephant in the room” says Vincent.

He starts by talking about network problems. Today, says Vincent, many companies outsource IT so thoroughly that there’s often no one on site to actively monitor network performance. Often, companies aren’t even aware that they have network problems and outsourced IT support is frequently passive; it responds only to trouble calls.

What you want, says Vincent, is active network monitoring to discover network problems quickly…perhaps even before the problem is noticeable. For example, Vincent cites one case where a company had more than 1000 active Ethernet ports in its network and there were transmission errors (excessive collisions, packet discards) on more than 20% of these ports. You want to guess whether that might cause a discernible network performance problem? Of course it does.

Often, says Vincent, these kinds of problems are caused by misconfigured ports. “How can they be misconfigured?” I ask. “Isn’t port configuration usually automatic?” I’m thinking of my own experiences where I plug the Cat-5 cables into the PC and router and “things just work.” Ah, says Vincent, some installers turn autoconfiguration off because they “know better.” Sometimes, even autonegotiation fails. You need to check the port to make sure it’s properly configured.

Vincent cites another case where a company had a modern, fast, 10Gbps network at its facility but 2Mbps pipes to remote offices running thin clients. You think that might cause a problem? Of course it does. The size of the problem depends on the task being performed. In Vincent’s experience, thin EDA clients can work—to a point. “However, it’s not for analog design or polygon pushing” he says. The classic rule of thumb is that thin EDA clients work if there’s less than 100 msec of latency in the connection. For layout tasks, make that less than 50 msec. Otherwise, the EDA tools will not feel appropriately interactive you you’ll get cranky designers.

Vincent then switches the topic to storage. Most large EDA customers have switched toNetApp storage, he says. Smaller customers try to save money, says Vincent, even to the point of buying consumer-grade storage at the local Best Buy. After all, it’s so cheap to buy that way. You get the clear impression in Vincent’s tone of voice that this is a “very bad idea.” Consumer-grade I/O for storage devices cannot provide the bandwidth required by EDA tasks, he explains. There might be as much as a 20x performance difference. So indeed, it is a bad idea.

Storage devices also provide opportunity for misconfiguration. Vincent cites the case of a storage system where the client company attempted to aggregate ports to a storage device to boost bandwidth. However, the aggregation wasn’t done correctly and instead of doubling the bandwidth by pairing the ports, the configuration was actually set up to alternate between the ports, adding needless delay because each packet transmission had to first find the right port to use.

Then Vincent switched to Linux. “If you’re on Red Hat 4, switch to version 5 immediately” he says. There are now way too many bugs to patch in version 4 at this point and many of those bugs are gone in version 5. Beyond that simple fix, Vincent has seen other types of Linux problems related to imaging consistency and root-access problems. To start with, buy consistent hardware he says. You don’t have to buy the latest and greatest servers but your hardware should be consistent. Otherwise, the Linux running on each server will need to be a little different. That will cause headaches.

“Consistency is the key” he says. Inconsistent hardware requires hand patching, which is never consistent. Use a kickstart server to start identical Linux images in all servers. That’s the only path to consistency, says Vincent.

Vincent concludes our discussion with a few more pointed suggestions:

1. Right now, servers based on the Intel Westmere-EP core provide a significant amount of performance boost to simulation—about a 30% increase. Vincent suspects it’s the particular mix of L1 and L2 processor cache that makes the difference.
2. Stay two to three firmware releases back on network and storage equipment unless there’s a known bug you need to fix with a firmware upgrade. Introducing firmware patches as soon as they become available puts your EDA infrastructure on the bleeding edge. That’s probably not a good place for EDA infrastructure.
3. Schedule two infrastructure maintenance windows per year (or at least one) to avoid unscheduled maintenance, also known as infrastructure crashes. It’s amazing how regular firmware upgrades and equipment reboots can clean out the cobwebs on a variety of infrastructure equipment. Memory leaks have not become extinct. Firmware needs to be upgraded. Deal with it.

Vincent is a senior member of the worldwide Cadence EDA Infrastructure Acceleration Services team managed by Paul Rose. He and the team help customers get more performance out of their EDA infrastructures. The team has done “hundreds” of “best practices shares,” which are 4-hour meetings with IT and CAD teams at EDA clients to discuss infrastructure-based EDA performance enhancements on general terms. He and the team have performed more than 50 assessments of EDA infrastructure systems to fix problems and boost performance. “We do this stuff all the time,” said Vincent.

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