Showing posts with label design. Show all posts
Showing posts with label design. Show all posts

Tuesday, October 16, 2012

EDA Mergers and Acquisitions Wiki - SemiWiki

Cool!  Accurate as far as I can tell, being a former member of Bell Labs Design Automation:


EDA Mergers and Acquisitions Wiki 

A Compilation of EDA Company Merger Listing All the Logos an EDA Company Owns
This list is a compilation over many years of mergers and acquisitions in the EDA market. The original compilation was done by an individual (Ian Getreu [1]) and is not an official list associated with any company or organization. Companies that have not bought or merged with other companies are not included in the list.

There is no guarantee of accuracy or completeness. Mergers and acquisitions that were not announced via press releases are probably not included. We welcome any additions and corrections.

The original objective was simply to list the number of logos owned by a company. So, if company A bought company B and was then bought by company C, this would be listed via indentations as:

Company C
Company A
Company B
(****SO**** means a Spin-Out)

Blog Article

ADELANTE TECHNOLOGIES
Philips Semiconductor DSP Division
Frontier Design
AGILENT (SO from HP in 1999)
EEsof (Acquired by HP in 1993, Touchstone product)
Alphabit (Momentum)
Eagleware (Genesys)
Elanix (SystemVue)
Xpedion Design Systems (July 28, 2006 - Terms not disclosed. GoldenGate RF IC simulation and analysis.)
Accelicon (December 1, 2011 - Terms not disclosed. 30 people. SPICE model analysis for model quality assurance.)
ALDEC

ALTERA
Right Track CAD
ALTIUM
NeuroCad Inc.
Logical Devices
INCASES Engineering GmbH
Protel International
Accolade Design Automation
MicroCode Engineering
Accel Technologies
Bought P-CAD and the Altium name from IBM 
IBM
(IBM sold mechanical CADAM to Dassault Systemes)
Changed name from CADAM to Altium
Microcadam
IBM CAD
P-CAD
Prance
After IBM sold its mechanical CADAM mainframe and workstation business to Dassault Systemes, the company changed its name from CADAM, Inc to Altium in order to avoid confusion with the product name CADAM. The remaining parts of the firm were Microcadam, IBM CAD, P-CAD and a joint venture in Japan. After the mechanical businesses split off, IBM sold Altium to Accel Technologies in 1995. Protel International acquired Accel in 2000 and in 2001 changed its name to Altium Limited
Green Mountain Design Automation
ICS Interactive (Innovative CAD Software)
Metamor Software
Tasking BV
Morfik Technology 
ANSYS
Ansoft (Acquired in 2008)
MacNeal-Schwendler Corp. (Electronics Business Unit)
Compact Software Inc.
Boulder Microwave Technologies
Pacific Numerix Inc.
Agilent's High Frequency Structure Simulator (HFSS)
Apache Design Solutions (Acquired June 29, 2011 for $310 Million in cash)
NSPICE
Baynacre
Optimal Corp
Sequence Design (Acquired September 8, 2009)
Frequency Technology
Sente Technology
nPower
Sapphire Design Automation
Posedge Inc
ARC INTERNATIONAL PLC
ARC Cores
Tenison Technology EDA Ltd.
MetaWare
ARM
Axys Design Automation
Artisan Components (renamed from VLSI Libraries)
Mentor Graphics' Physical Product Line
Synopsys Physical Libraries Business
NurLogic design
Obsidian Software (17 June 2011)
Prolific Inc. - IC design optimization tools: ProGenesis, ProTiming, ProPower, ProDFMOptimizer. Founded in 1995 by Dr. Paul de Dood. Acquired November 1, 2011, terms not disclosed.
ASIC ALLIANCE
CadWorx Consulting
ASML Holding NV (with these acquisitions ASML is now also in the EDA world)
Brion Technologies Inc.
Masktools Inc.
ASPEC
Verilux Design Technology Inc
Chip & Chip Technologies Inc
Novo Systems Corp (formerly Zycad TSSI)
inBox
ATRENTA
AXIOM Design Automation
New name for @HDL
NextOp Software Inc. (assertion synthesis, June 20, 2012 - terms not disclosed)
AZINI CAPITAL
OneSpin Solutions - formal assertion-based verification tools. January 24, 2011.
BARCELONA DESIGN, INC (Out of business in March 2005. Spent $44M in venture capital, had Joe Costello as Board Member. Similar Analog IP technology as Sabio Labs, now part of Magma.)

CADENCE
SDA (Solomon Design Automation)
ECAD (Dracula)
PDS (Phoenix Data Systems)
Simon (Simulator)
Tangent Systems (Layout)
Sedco (Schematic-symbol generation)
Pinebush Technologies
Gateway (Verilog)
XCAT
ASI (PCB Layout)
UniCAD
Helios (Thermal tool)
Seed VHDL Environment (VHDL simulator - Leapfrog)
Alta Group (ESDA)
Comdisco (ESDA) ------à SPW product line to CoWare
ST*AR (BONES network simulator)
Redwood (ESDA)
Synthesia (Synthesis)
Systems & Networks Inc (Sales arm for Comdisco tools)
Spectrum Services (Consulting)
Advanced Microelectronics (Consulting)
Columbia Design Center (Consulting)
Unisys (STO) (Consulting - ASIC)
HLD (IC Floor Planning)
Cooper & Chyan Technologies (PCB Layout) (1997, $418M, CEO interview)
UniCAD (Layout)
Valid
ADT (Analog Tools)
GE (the division of GE that bought Calma)
Calma (Bought Comsat's simulator business)
Comsat (Bought Tegas)
CCSS (Tegas Logic Simulator)
Tegas Inc (Tegas Support) 
***SO*** IMS (Test)
Telesis (Test and simulation)
Parsec (Timing analysis)
Intermetrics (VHDL test suite)
Wyoming (?)
Synthesia (RTL Synthesis)
Symbionics Ltd. (Design consultants)
Excellent Design Inc (Design consultants)
EXD Technologies Inc. (Design consultants)
Esperan (EDA Training)
Detente (Software Development)
Ambit Design Systems (Synthesis) (1998, $260M)
Bell Labs Design Automation (Simulation, Verification)
Quickturn (Emulation)
SpeedSim
Arkos Div of Synopsys
PIE Design Systems
Mitsui Bussan Digital's emulation business
Design Acceleration Inc (DAI) (Simulation)
***SO*** Alchemy (Design consulting)
***SO*** Accent (Design services)
Orcad (PCB Design)
EDA Bridge from T.E.A.M
Q Point Technology (CIS features)
Microsim (Analog simulation - PSPICE)
Intelligent Systems (Japan Distribution)
Massteck Ltd. (PCB Layout)
ARS Microsystems (UK Distribution)
Diablo Research Company LLC (Design consultants)
***SO*** Tality (Design consulting)
***SO*** SpinCircuit (brought back in)
------->SpinCircuit (Design Services)
Westport Technologies (Design Services - Telecom)
CadMOS (Signal Integrity)
Apres Technologies (assets)
Silicon Perspective Corp (Vitual Prototyping)
Plato Design Systems (IC Router)
Simplex Solutions (Verification)
Snaketech
Altius Solutions Inc
Coyote Systems IP assets from Coventor Inc.
IBM's Design-for-Test Tools Business
Antrim Design Systems assets
Celestry
Ultima Technology
BTA Technology
Get2Chip
Meropa (renamed as Get2Chip)
K2 technologies Inc. (acquired May 7, 2003 - terms not disclosed. Products: K2-MaskCompose, K2-Chameleon, K2-QuickView. Technology came from TI.)
Verplex Systems (acquired July 16, 2003 - terms not disclosed. Products: Conformal LEC logic equivalence checker, Conformal LTX logic transistor extractor, Conformal FPGA equivalence checker, Conformal LVR layout versus RTL, Conformal MEM memory equivalence checker, Conformal Datapath circuitry checker, and BlackTie.)
Q Design Automation (Process migration)
Neolinear (AMS & RF)
Verisity (Test, was named InSpec)
SureFire Verification Inc. (was named Silicon Sorcery)
Axis Systems
Praesegus Inc (DFM)
CommandCAD (DFM)
Invarium Inc (Pattern synthesis)
Clear Shape Technology (DFM)
Chip Estimate Corp (IC planning and IP reuse)
Beach Solutions
VCX Software Limited
Knowlent assets
Nascentric (FastSPICE circuit simulator called AuSIM, parallel simulation, GPU-powered version. Acquired by Cadence in 2009, terms not disclosed)
Taray (FPGA)
Denali (Memory IP, acquired May 2010)
Altos Design Automation (Library Characterization, Press Release: May 10, 2011)
eTop Design Automation (Masco Physical Verifier, became known as PVS, Acquired in 2004)
***SO*** ProPlus (people came from Celestry. Analog simulation)
Azuro (Clock Concurrent Optimization, Press Release: July 12, 2011, amount not disclosed)
SIGRITY (Announced July 2, 2012. Signal and Power integrity analysis. $80M deal.)
Encore Technology (from Synopsys)
CALYPTO
Catapult C (Spin out from Mentor Graphics, August 26, 2011, amount not disclosed)
CARBON
Axys (from ARM)
CAST
Lineage Systems Inc
C LEVEL DESIGN (renamed from Compilogic)
Transmodeling Inc
CLK DESIGN AUTOMATION
Synchronous Design Automation
CYNERGY SYSTEM DESIGN
CAE Plus
DANIHER
Tektronix
TDA Systems
DASSAULT SYSTEMS
MatrixOne
Synchronicity Software
IPinfraNET product from Cadence
Elsys (electrical PLM, Products: electre, catelectre, smartelectre. October 26th, 2011 - terms not disclosed.)
DOULOG
Beach Solutions
ELECTRONIC WORKBENCH
Interactive Image Technologies (rename)
Ultimate Technologies
EMA DESIGN AUTOMATION
Chronology Division from Forte Design Automation
Design Advance
ENTROPIC
Vativ
ESSENSIUM NV
Mind NV
EVE
Tharas Systems
EXPRESSIVE SYSTEMS INC
Vizef

FORTE DESIGN AUTOMATION
Chronology Inc à EMA Design Automation
CynApps (was named C2 Design Automation)
Arithmatica
GATEFIELD (renamed from Zycad, August 1997)
Zycad
Integrated circuit Applications (InCA)
Silicon Solutions
sold fault-acceleration to Ikos Systems 
Attest Software Inc.
ExperTest sold fault-simulation to Credence/TSSI, sold to Aspec
GENEDAX
Expressive Systems Inc.
GENNUM CORP
Snowbush Electronics 
HELLMAN & FRIEDMAN, TEXAS PACIFIC GROUP
Intergraph
HP-MICROWAVE
HP
Eesof
Optimization Systems Associates Inc.
ICERA
Sirific Wireless
INTEL
Wind River
Virtutech
CoFluent Design (CoFluent Studio EDA, acquired September 13, 2011, amount undisclosed, founded in 2003).
INTERCEPT
Harris EDA's PC Board tools
JASPER DESIGN AUTOMATION
Safelogic
JAVELIN DESIGN AUTOMATION
Icinergy Software (assets)
JUNIPER NETWORKS
Micro Magic Inc.
------ Spun back out
KEY ASIC (new name for Arcadia)
ARCADIA DESIGN SYSTEMS
SiliconX
MacNEAL-SCHWENDLER
MacNeal-Schwendler
Automotive Analytics

MEMSCAP
Cronos Integrated Microsystems Inc
Mentor Graphics
CADI (Board Layout)
Caedent (Logic Simulator)
Contour/Acotech (Analog Libraries)
Synergy Dataworks (Hardware accelerator)
Context (Documentation)
Trimeter (Synthesis)
Tektronix CAE (CAE)
VR Info Systems (Standard Cell Layout)
CAE Systems (CAE)
Tektronix CASE (CASE)
Performance CAD (Timing analyzer)
Parade (Small FPGLA)
Checklogic (ATPG)
Silicon Compiler Systems (SCS)
Silicon Design Labs (Generator Development Tools, Lsim)
SCI (Silicon Compilers Inc - Genesil)
Caeco (CAE)
Descartes (P&R)
EDC (Silvar-Lisco's European R&D)
TI (CheckMate - LVS, MaskPE - LPE)
Anacad (Analog simulation)
EES (Analog simulation)
Egypt Model Technology (Analog modeling)
Axiom Daterer Skandinavien (Schematic-symbol generation)
Meta-Systems (Logic emulation)
Microtec Research (Embedded systems)
Hunter & Ready (Real-time OS software)
ONE (Network management tool)
Precedence (Backplane)
Zeelan Technology (Signal Integrity Models)
----------------> Z2 Consulting LLC (SO)
Integrity Engineering (Signal Integrity Simulation)
3Soft (Digital models)
CoSoft (PC Schematic Entry)

SETO Software GmbH (PCB layout)
Interconnectix (Interconnection synthesis)
Royal Digital Centers Inc (PCB - manufacturing links)
dQdt (DSP function blocks)
Systolic Technology Ltd. (Telecomm blocks)
Open Networks Engineering (Telecomm blocks)
CAE Technology Inc. (Peripheral controllers blocks)
CLK Computer-Aided Design Inc. (Timing-driven placement & optimization)
OPC Technology (Optical proximity correction software)
Veribest (part of Intergraph)
M&S Computing
DAZIX
Daisy Systems
Cadnetix
HHB
Shiva
Vizef
---------------> Physical Library Division to Virage Logic
Escalade (ASIC HDL graphical design tools)
Descon Informationssysteme GmbH (Product Data Management)
HLS (High-level synthesis)
CADIX ECAD Division (Printed Circuit Board)
Antares 
Model Technology (VHDL Simulator)
Exemplar (Digital Synthesis)
Harness Software Group (Harness Software)
SpeedGate Design Automation (Emulation)
Capital H (Wire Harness)
Accelerated Technology (RTOS)
Ikos (Hardware Emulation)
Racal Redac (VHDL Simulator)
Virtual Machines
Zycad (Emulator, August 1997)
Interra
Delsoft (India)
Deerbrook Systems
Innoveda (Systems)
Summit ---------------------------> Summit Design
TSSI -------------------> Credence
SEE Technologies
TriQuest Design Automation
Simulation Technologies
Viewlogic
Transcendent Design Technology
PADS Software
HyperLynx
ACT (Advanced CAM Technologies)
Assets of DDE-EDA A/S, (PCB packaging)
Alcatel's Ethernet & MAC IP business (IP)
FirstEarth (Wiring)
Project Technology (UML tools)
0-in Design Automation (Verification)
Atair GmbH (Compiler)
Palmchip Parallel & Serial ATA IP business (IP)
EverCAD Software (Fast SPICE simulator)
Volcano Communications Technologies (Automotive network design tools)
Aptix (Emulation)
--------------------------------------- Cre8Ventures (UK company supporting users)
Summit Design (ESL)
SpiraTech Ltd (ESL)
Sierra Design Automation (Place & Route)
NXP Semiconductor DFT tools and people
Assets of Ponte Solutions Inc (DFM)
Flomerics Group (Thermal analysis)
C Synthesis assets of Agility Design Solutions
Catalytic (name change)
Celoxica Holdings ESL business
Logicvision
SiVerion
Embedded Alley Solutions
Valor Computerized Systems (PCB)
Zeland (3D field solver)
Virtual Garage (from Freescale) (Automotive tradeoffs)
Valor Computerized Systems Ltd (PCB)
Pextra (3D Field Simulation, acquired in 2010?)
Pyxis (Custom IC routing, acquired Q3 2010)
CodeSourcery Inc assets (Open-source tool chains for system development, acquired Dec 10 , 2010)
Flowmaster Group (computational fluid dynamics simulation software, terms not disclosed, announced January 9, 2012)
METHODICS
Missing Link Tools (EVOLVE - Agile framework for build, test, regressions. Terms not disclosed. May 31, 2012)
MICROCOSM TECHNOLOGIES
Coyote Systems
MICRO MAGIC
(Spun back out from Juniper)
MINC
Futurenet
ENDOT
Synario
MIPS TECHNOLOGIES
Chipidea Microelectronics SA
NATIONAL INSTRUMENTS
Electronics Workbench
AWR (High frequency tools, $58M, Announced on May 23, 2011)
Accolade from I/Q Com Corp
--------------> SO as Visual System Simulator
APLAC
OPEN-SILICON INC
Zenasis Technology IP assets (Zenasis folds)
PARAMETRIC TECHNOLOGY CORPORATION
OHIO Design Automation Inc
PDF SOLUTIONS
IDS Software Systems
WAMA Technology from WaferYield Inc
Si Automation SA
Fabbrix Inc
POLICYONE
Duet Technologies (was named Software & Technologies)
CrossCheck Technology
Aida (from Teradyne EDA)
Cascade Design
TunnelNet
PRECIENCE
Technology Solutions Inc (Pakistan)
QUALCORE LOGIC
LEDA Systems Inc.
QUALCOMM
Rapid Bridge (LiquidCell Library, announced June 13, 2011. Terms not disclosed.)
SAGANTEC
NP-Komplete Technologies (May 3, 2012 - terms not disclosed)
SEVA TECHNOLOGIES
Intrinsix Inc

SILICON AND SOFTWARE SYSTEMS (S3)
Acacia Semiconductor SA
SILICON VALLEY RESEARCH (SVR)
Silvar Lisco
Quality I.C.
SILVACO
Simucad (Spin-out from Silvaco in June 2004, merged back into Silvaco, Inc. in March 2010)
Space Codesign

SynaptiCAD
Right to sell ASC tools
Synopsys
OSI (spin-out from GE)
Zycad's simulator
(Data I/O
Futurenet
ENDOT)
Compiled Designs
SC High Tech (Japanese distributor)
Cadis
Logic Modeling
LAI
LMC
LMSI
Silicon West
Quadtree
Arcad
Silicon Architects
Arkos Design
Excelsior Research (investment, not purchase)
Epic Design Technology
Archer Systems
Cida
VLSI Libraries (10% stake, not ownership)
(Viewlogic)
Vantage
Abstract????
Racal-Redac parts
Quad Design
Sunrise Test
ExperTest
Chronologic Simulation
Silerity
EDAS Europe BV, The CAE Co. BV
Transfer Electronic Design Support
Eagle Design Automation
Radiant Systems
Everest Design Automation
CoverMeter
Smartech Oy
Gambit Automated Design
Apteq
Stanza
Systems Science
VirSim
TSG
LEDA S.A.
The Silicon Group
C Level Design Inc assets (not the company)
Avant!
Arcsys + ISS (Merger announced August 22, 1995 forming Avant!)
Psi
Anagram
Meta-Software (HSPICE)
MasterToolBox company
Frontline Design Automation
Nexsyn
--------------------> AvanWise
Compass
CLSI Solutions
--------------------> Galax!
Technology Modeling Associates (TMA)
Precim
Datalink Far East Ltd.
Arcus Technology
ACEO Technology
interHDL
Xynetics Design Systems
Harris EDA (rename)
Chrysalis Symbolic Design
Analogy
Symmetry Design
inSilicon
Xentec
Phoenix Technologies (spun out InSilicon)
Sand Microelectronics
Virtual Chips
RAVIcad (renamed as Virtual Chips)
Co-Design Automation
Numerical Technologies Inc.
Transcription Enterprises Ltd.
Cadabra Design Automation
Qualis verification IP assets
Innologic Systems Inc.
Analog Design Automation
Accelerant Networks
Memory BIST Division of iRoC Technologies
Integrated Systems Engineering (ISE)
Monterey Design Systems (assets)
Aristo Technology
Cascade Semiconductor Solutions (also known as Cascade IP)
LEDA Design (assets)
Nassda
The staff of Zeta Infotech
HPL Technologies
----------------- Encore technology (sold to Sigrity)
Virtio
Sigma-C AG
ArchPro Design Automation
MOSAID Semiconductor IP assets
Sandwork Design Inc
Synplicity
Iota Technology Inc signal integrity & power analysis technology
Bridges2Silicon Inc.
HARDI Electronics AB
ProDesign’s CHIPit Business Unit
MIPS Technologies Analog Business Group
ChipIdea Microelectronica SA
VaST Systems Technology Corporation (Announced Feb 2, 2010, terms not disclosed)
Gemini Design Automation (GSim - a SPICE circuit simulator. Reported March 11, 2010. Terms not disclosed. Founded in 2005.)
CoWare Inc (announced Feb 8, 2010, terms not disclosed)
Comdisco SPW product line (from Cadence)
LisaTek Inc
Virage Logic Corp (Announced June 10, 2010 for $315 million. Semiconductor IP.)
Mentor Graphic's Physical Library Division
Impinj NVM IP business
NuSym Technology (Announced June 28, 2010. Terms not disclosed. Intelligent testbench technlogy.)
NXP Semiconductor IP
Synfora assets
Esterel Studio from Esterel EDA Technologies (France)
Optical Research Associates

nSys (Verification IP, September 2, 2011, price not disclosed)

Extreme DA (Acquired October 6, 2011, terms not disclosed. Statistical Static Timing Analyzer - GoldTime)
Xigmix
MAGMA DESIGN AUTOMATION (Acquired November 30, 2011. Priced at $507M or $7.35 per share.)

Moscape
Aplus Design Technologies
Silicon Metrics (2003, $32M, Press Release, Press Release)
Random Logic (2003, $25M, Press Release)
Mojave Design
VeraTest
PDAT
ReShape (assets)
ACAD
Knights Technology (from FEI)
Rio Design Automation
Sabio Labs


ExpertIO (Announced January 23, 2012. Verification IP. Terms not disclosed.)
Inventure (Announced January 24, 2012. A subsidiary of Zuken, Japan. Interface IP. Terms not disclosed.)
RSoft Design Group (Announced May 9, 2012. Photonics design and simulation software. Terms not disclosed.)
Ciranova (Announced July 30, 2012. Analog IC layout automation tools: Helix, PyCell, Pyros Viewer. Terms not disclosed. Blog by Daniel Payne.)
SPRINGSOFT INC (Announced August 3, 2012. $305M cash deal. Blogs by Daniel Payne, Paul.)
Novas Software
Silicon Canvas
Fortelink
Novaflow
Nanovata
Certess
TELA INNOVATIONS INC
BLAZE DFM 
Aprio
TNI-VALIOSYS SA
Arexsys SA
Techniques Nouvelle d'Informatique SA (TNI)
TransEDA
DualSoft
iModl Inc
TransEDA SYSTEMS
Sold by Valiosys
TANNER
TEKTRONIX
Veridae (ASIC/FPGA prototyping, announced July 5, 2011. Terms not disclosed.)
TERADYNE EDA
Aida (ATPG, HW & SW simulation, STA)
Case Technology (Schematic capture, PCB layout, simulation)
VIGILANT SYSTEMS
EDAConnect
Javelin EDA
VALIOSYS
TransEDA
VERIGY
Credence
Fluence Technology
TSSI
xxx (California company)
xxx (California company)
Opmaxx
Tektronix's Test Business
New Millenia Solutions Inc
Integrated Measurement Solutions
NPTest
LTX
XILINX
Neocad
Visual Software Solutions & formal-verification technology from Veriphia
Hier Design
AccelChip
Bit-tru
MINC
IST
AutoESL Design Technologies - High level synthesis tools, acquired January 31, 2011
XtremeEDA Corp
ESLX Inc
ZUKEN-REDAC
Zuken
Racal-Redac
Racal
Redac
Thom6
Silc
HHB
Simucad
Shiva
Incases Engineering GmbH
INCASES North America Inc.
CIM-Team GmbH
ZYCAD
Silicon Solutions

[hide] - [top]Footnotes

  1.  ^ Ian Getreu, IG Associates,(503) 888-2372




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Created by
, 01-16-2011 at 09:17 PM
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, 08-03-2012 at 01:04 PM
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EDA Mergers and Acquisitions Wiki - SemiWiki

'via Blog this'

Monday, October 1, 2012

Why Hardware Doesn’t Fit the Agile Model | AgileSoC (Guest Blog: A Heretic Speaks)

Guest Blog: A Heretic Speaks (Why Hardware Doesn’t Fit the Agile Model)

Fair to say that what we’ve posted on AgileSoC.com to date is decidedly pro-agile. Bryan, myself and the guest bloggers we’ve had thus far believe in agile hardware development so we haven’t spend much time talking about why agile hardware wouldn’t work. No surprise there. But when you’re getting a steady diet of opinions from one side of an argument, it can be easy to forget that there can be some very practical arguments on the flip side to the coin. Today – after a little cajoling from Bryan over the past year – Mike Thompson from Huawei in Ottawa brings a little balance to AgileSoC.com by examining the flip side of the coin.
In A Heretic Speaks, Mike talks about reasons why agile and hardware just don’t go together. Being that Mike brings years of knowledge to the discussion, it’s hard to call this anything but a fair assessment. But I’d love to know what you think. Do you agree with Mike’s assessment? Extra points to those involved with physical design that jump into the discussion!
Take it away, Mike!

A Heretic Speaks

For a couple of years now, I’ve been reading the AgileSoC blogs.  They are great reading, and each update provides an opportunity to see SoC development from a different perspective.  Every now and then a tidbit from one of the blog entries you’ll find at this site will make its way into my own work – which is probably the whole point.  Having said that, I simply do not agree with the idea that the Agile software development model can be applied to SoC development.   There.  I said it.   I can feel the virtual slings and arrows of an outraged Agile community allied against me.  :)
There is a contraction in what I just said.  If I do not believe that Agile can be applied to SoC development, then why do I continue to read this blog and even adopt some of the concepts discussed here?  The answer is simple: I am Verification geek and more-and-more SoC verification has become a software activity.  So Agile can teach verifiers a thing or two about their craft.  However, apart from Verification, SoC development is not software development.   SoC development is hardware development.  That distinction is real and it matters.

Hardware is not Software

As Verifiers, our view of the overall SoC[1] development cycle can be somewhat stunted.  Our view of the design is mostly formed by our interactions with the RTL and the designers who write the RTL.  Of course, RTL is just a specific type of software right?  It can be compiled into an executable for simulation, or it can be synthesized into a gate-level model that can be mapped onto a netlist of logic cells from a library.  Sounds like software to me.  The trouble is, RTL is just the tip of the iceberg.  It’s the part of the design that is the easiest for us to see, but it is not all there is to the design – and it’s not the biggest part – not by a long shot.  Let’s have a look at a few reasons why.

Hardware is not Virtual

One of the coolest features of software is that it can use virtual resources.  Need more memory – just call malloc()!  Need another object – just call new()!  We do this all the time in Verification.  Heck, if you are a SystemVerilog user, you can even have virtual interfaces.  You can’t do this in hardware.  All resources – the amount and type of memory needed, the number and type of interfaces, the amount of logic to perform tasks – all of this is fixed and is not easily changed.  Why?   Because you are building hardware and all of these resources are physical.  Worse, all of them cost money.  Before your organization lets you build a chip, the-powers-that-be will want to know what it costs.  As in how-many-dollars-per-chip?  In order to answer this question, you’ll need to answer to a bunch of important questions such as what process node you will use (e.g 32nm) and how big the die will be (e.g. 10mm x 10mm).  In order to answer those questions, you’ll need to know things like how many and how big the I/O interface macros are (e.g. high-speed SerDes and DDR PHYs), and the types and geometries of memories you can use.   In short, you will need to know a lot about your design.  And you’ll need to know it long before you start writing any RTL.   This is one of the reasons that Test Driven Development (TDD) doesn’t fix RTL coding very well… but I’m getting ahead of myself…

RTL is not Abstract

Describing digital logic at the Register Transfer Level is probably the single biggest advance in hardware development ever.  RTL reduces effort and improves quality by allowing digital logic to be described at a functional, as opposed to structural, level of abstraction.  But it’s not that abstract – not really.  An RTL designer still needs to understand and deal with clocks, resets, complex interfaces to memories, clock gating and clock-domain-crossings.   She needs to know how many levels of logic she can get away with between flops; which are a function of clock period and the cell library.  Also, RTL doesn’t allow designers to explicitly control things like area, timing and power.  A lot of very fancy tools have been deployed to improve this situation, but for the most part, getting all this right still involves a lot of blood, sweat and tears.   The implication here is that designers often spend more time on structural issues, such as clock-domain crossings and clock-gating, than they do on functional issues.  Strike 2 for TDD…

Physical Design Takes a Loooong Time

One of the biggest differences between software and hardware is how they are mapped into a product that actually does something useful.  Software is compiled.  For a large software product (tens of millions of lines of code), a compile/build cycle can be many hours or days.  Long enough, but not too bad and most of it is fully-automated.  The implication is that software can cut a release at just about any time.  The equivalent task in SoC development is called Physical Design, and it’s a big task.  For a large SoC (tens of millions of gates), the physical design – getting from that netlist to working hardware – can be several weeks or even months.   To get it right, several iterations may be required.  Much of the work cannot be automated.  The implication here is that SoC development time is driven primarily by Physical Design, not Functional Verification.  The PD cycle is set very early on in the project and it is extremely difficult, if not impossible, to change it.  One of the things a good Program Manager will try to do is fit the Verification cycle entirely within the PD cycle, so that Verification doesn’t drive the schedule’s critical path[2].

Why Hardware Doesn’t Fit the Agile Model

OK, hopefully by now you’re convinced that hardware development is a distinct task from software development, and SoC development is mostly a hardware development activity.   That still doesn’t explain why Agile can’t be applied to SoC development.  I’ll try to do that by making reference to a couple of AgileSoC posts from last year: “When Done Actually Means DONE” and “TDD And A New Paradigm For Hardware Verification”.

You’re not Done until PD Say you’re DONE.

In “When Done Actually Means DONE”, a contrast is made between the Waterfall development model and the Agile model:
Figure 1: Waterfall vs. Agile Development Models
I doubt that anyone is working on a team that is using the waterfall model anymore.  All development teams that were doing this have long ago gone out of business because their products were either very late to market, full of defects, or both.   The Agile model is much better – except that it doesn’t work for hardware.  There are a couple of big reasons why this is so.  First, since hardware is not virtual, some aspects of the physical design must start first.   Yes, even before the Specification and certainly before the RTL coding.  Second, the pace of the development is set by PD.  This effectively negates one of the biggest advantages of Agile development: the ability to quit development and generate a release of your product whenever it suits the project.
So most large SoC projects look more like a hybrid of the Waterfall and Agile methods as shown in Figure 2.   Let’s call this model “Concurrent Engineering”.   Now you could say that this is a visual description of how SoC development can take advantage of some aspects of Agile development.  Getting rid of that waterfall and replacing it with concurrent tasks really does improve quality and reduce schedules.   But we cannot build the SoC at the 50% mark.  Software can do that.  Not hardware.
Figure 2: Concurrent Engineering of SoC Tasks

TDD is not a good fit for RTL coding

In Figure 2, the RTL coding task has been explicitly broken out.  This was done to illustrate an important point that was alluded to earlier: designers actually do not spend that much time coding RTL.  There are two big reasons for this:
  1. Most of the real design work such as spec’ing out memories, clocking, resets, resource allocation/management, etc. must be done before RTL coding starts.
  2. In order to begin PD trials, the bulk of the RTL must be available early – long before it is fully verified.  This is an important point: at this stage, the RTL need not be functionally correct, but it must be ‘complete’ in that all functions are implemented[3].
So, the actual RTL coding doesn’t take that much time (3 to 6 weeks is typical).  Given that, a Test Driven Development (TDD) process for RTL is a bad idea since it slows done the delivery of the code that is needed for PD.  Note that this is not true for the verification code.  TDD for testbenches, testcases, coverage models, etc. is very beneficial and should be part of all verification flows[4].

Conclusion

Well, if you’ve gotten this far then you are pretty open minded.   After all, if you are even a semi-regular reader of this blog, then you probably think Agile is a pretty darn good idea.  I do too – but just not for the hardware side of SoC development.   For Verification and Emulation, it’s a different matter.  In our Verification shop we cherry pick many Agile concepts (such as unit-testing of verification code and continuous integration of the verification environment and RTL) and for Emulation we pretty much go all out with Agile.  So I hope that this blog continues to be an open forum for applying Agile to these activities.
Thanks to Neil for setting up this blog and continuing to drive it, and special thanks for permission to re-use his slide from “When Done Actually Means DONE”.  Not many people have the self-confidence to provide ammo for the opposition in a public forum.  J  Also, if you haven’t already – get a copy of SVUNIT and use it!
–Michael Thompson
   ASIC Verification Manager
   Huawei Technologies
   Ottawa, Ontario, Canada
   michael.thompson@huawei.com

[1] Actually, I’d prefer to use the term “integrated circuit” or “IC” in this discussion.  By “IC”, I mean any large scale integrated circuit implemented as an ASIC or ASSP.  However, SoC is used throughout this site, so I’ll continue to use the term, or sometimes I’ll just say “chip”.
[2] I know, I know.  It is rarely possible to keep Verification off the critical path for at least part of the project.
[3] It shouldn’t be brain-dead either.  In our shop, PD trials start on a netlist that has passed at least some basic functional testing.
[4] If you do not already have a methodology in-house of TDD of your verification code, I strongly recommend that you take a good look at SVUNIT.

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