Oski Technology Beats 72-Hour Clock in Formal Verification Challenge - Yahoo! Finance

To be fair, Vigyan and his team are likely what I would call "expert formal users", but still a pretty cool feat...    :-)

Oski Technology Beats 72-Hour Clock in Formal Verification Challenge

Formally Verifies NVIDIA Design in Three Days, Finding Four Corner-Case Bugs

Press Release: Oski Technology – Wed, Sep 12, 2012 11:30 AM EDT

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MOUNTAIN VIEW, CA--(Marketwire - Sep 12, 2012) - Formal verification services provider Oski Technology (www.oskitech.com) is celebrating success after beating the 72-hour clock in the first-ever Oski Verification Challenge held during this year's Design Automation Conference (DAC) in June.

"We showed that formal verification is a proven technology," affirms Vigyan Singhal, Oski's president and chief executive officer, whose team successfully delivered formal verification results on a new NVIDIA design in less than three days. "This was an ambitious project and one that hasn't been attempted before at DAC, but we were confident in our abilities and the formal verification methodology."

The Oski team received a register transfer level (RTL) design it hadn't seen before from NVIDIA at 5 p.m. Sunday, June 3, hours before DAC officially began, and formally verified it in less than 72 hours. DAC attendees followed the action on a webcam feed at the Oski booth and through regular Twitter updates.

Announced in March, the Oski Verification Challenge invited design teams to provide an RTL design of any type, including legacy design, in any design phase. NVIDIA's design was selected, though not shared with Oski until the challenge began, though the two companies worked together to determine what information would be most suitable for a summary report.

The NVIDIA team received a detailed verification report delivered at 5 p.m. Wednesday, June 6, showing four formerly undetected corner-case bugs. Additionally, the Oski Verification Challenge team wrote and identified end-to-end checkers, some of which were passing.

Anshu Nadkarni, NVIDIA's director of hardware engineering, notes: "I believed something would come out of the formal verification challenge, but the result exceeded my expectations. The end-to-end verification is extremely valuable for us. We have tight deadlines and aggressive schedules. The micro-architecture is detailed, making it hard to come up with a comprehensive verification plan without understanding it. What Oski Technology was able to achieve is phenomenal."

Each NVIDIA team member was awarded a Time-to-Verify certificate, a digital photograph with the Oski engineering staff, and an Oski Live Verification Challenge T-shirt.

To learn more about the Oski Verification Challenge, visit: http://oskitech.com/2012/09/oski-challengewrap-up-video/.

About Oski Technology

Oski Technology is a formal verification services company with expertise in deploying formal verification on complex, digital designs. Oski Technology has developed a unique formal verification methodology and Oski Abstraction Models to solve challenging capacity problems with formal verification. Its formal methods bring a higher level of productivity than traditional simulation and formal verification approaches. Oski Technology, headquartered in Mountain View, Calif., with a design center in India, has built a team of the world's foremost experts in formal verification. More information about Oski Technology can be found at: www.oskitech.com.

All trademarks and registered trademarks are the property of their respective owners.

Contact:

For more information, contact:
Nanette Collins
Public Relations for Oski Technology
(617) 437-1822
Email Contact

Oski Technology Beats 72-Hour Clock in Formal Verification Challenge - Yahoo! Finance

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Using formal “apps” to automate IC verification

Webinar Report: How Formal “Apps” Ease IC Verification

By Richard Goering on August 16, 2012Comments(0)Filed under: Industry Insights, IP-XACT, verification, Incisive, IEV, Formal Analysis, IFV, VIP, webinar, assertions, ABV,assertion-based verification, formal verification, properties, code coverage, formal scoreboard, Mueller, Rubik's cube, Lego robot, reachability, Hupcey, formal apps, register map, protocol compliance, SoC connectivity, Sudoku, linting, formal applications, functional verificatioin, ABVIPFormal verification applications, or "apps," can significantly lighten the IC verification workload without requiring a knowledge of assertion-based verification (ABV) - or even, in most cases, the need to write assertions. A recently archived Cadence webinar, held Aug. 8, 2012, describes some helpful formal apps and encourages users to build their own.
The webinar, titled "Formal Apps to Automate Mainstream Verification Challenges," was presented by Joseph Hupcey III, product marketing director at Cadence, and Joerg Mueller, staff solutions engineer at Cadence. It is part of an ongoing series of free functional verification webinars that will run through mid-December.
Hupcey began the webinar by talking about the challenges that have limited the adoption of formal and ABV technologies. He noted that many engineers do not want to learn about assertion languages, that most engineers do not want to learn about formal techniques, and that verification leads have trouble showing the value of formal in the context of a full project. While there's an assumption that it takes a PhD to run formal verification, "that's not true today, and we'll show you a way to automate that away completely," Hupcey said.
What's a Formal App?
In a general sense, Mueller said, an app runs on a platform - in this case, on Cadence Incisive Formal Verifieror Incisive Enterprise Verifier. He offered this three-part definition of a formal app:

• A well-documented tool capability or methodology focused on a specific, high-value problem
• The problem is more efficiently solved using formal methods than using simulation-based methods
• The need to create properties or have ABV knowledge is significantly reduced, because properties can be generated automatically or provided in a pre-packaged form

The webinar then described the formal apps depicted below. As the chart shows, formal apps can be used at different stages of the project life cycle, from early RTL development to system tapeout.

Formal apps across the project life cycle Automatic Formal Analysis and Super Linting
The top two apps identified on the chart work together to provide an advanced linting solution in which properties are generated directly from the implied behavior of the RTL. This is needed because designers generally do not provide adequate verification for the code they write. An HDL analysis linting capability links checks and messages back to the source code. Automatic formal analysis automatically provides checks for such concerns as dead code, finite state machine, pragmas, X states, busses, range overflow, and toggling. HDL analysis linting combined with automatic formal analysis results in "Super Linting."
Protocol Compliance
Protocols are well-defined in written specifications, but what we need to verify against is an executable specification. The solution is to use pre-packaged properties along with assertion-based verification IP (ABVIP) for a given protocol. Cadence now provides ABVIP for major AMBA protocols and for OCP, and it can be used in both simulation and formal verification. Protocol-aware debug, now available in the Cadence SimVision user interface, offers protocol-specific transaction-level debugging. The webinar includes a demo.
Formal Scoreboard
Formal verification has historically been targeted only to control-oriented functionality, but data transport checking is actually a "sweet spot" for formal technology, according to Mueller. The solution is to provide a set of pre-packaged properties that are tuned for data transport checking using sequences of symbols. The basic idea is to force (or constrain) a sequence of input values, and check (assert) that the same sequence appears on the output. Cadence Incisive Formal Verifier and Incisive Enterprise Verifier provide a Formal Scoreboard Template that can help with this task.
Code Coverage Unreachability
This is "probably the fastest growing formal app that we see in the marketplace at the moment," according to Mueller. The problem is that holes in code coverage can take weeks to analyze manually. If you can sort out unreachable (impossible to hit) coverage holes, the task will be easier. This formal app analyzes whether uncovered code is reachable (in which case the test suite is insufficient) or unreachable (solved by fixing RTL or discarding the hole). A demo shows that this process is fully automatic and that users don't even see the formal tool running.
(Note: A user case study of a code coverage unreachability formal app is provided in an archived CDNLive! India 2011 paper by Freescale. )
Register Map Validation
All too often, simulation insufficiently checks for correct register map access and absence of corruption. A formal app can generate properties automatically from an IP-XACT specification, and greatly simplify the register map validation flow. The assertions can check value after reset, register access policies, and the use of write-read sequences with front door and back door access.
SoC Connectivity
This is the oldest and most mature formal app, in production since 2005, Mueller said. It automatically generates properties from the connectivity specification in order to quickly and efficiently verify IP integration. The spec defines internal connections as well as external connections to and from I/O pads. The app provides forms and wizards to ease specification entry and import into a spreadsheet, lets users import results from analysis, and offers built-in connectivity "linting." A demo shows how to edit a spreadsheet, run connectivity checks, debug a failure, and back-annotate results to the spreadsheet.
Dream Your Own!
"What we want to encourage you to do now," Mueller concluded, "is to dream up your own formal apps. Look for verification problems that are boring, repetitive, or inefficient with simulation because it is difficult or tedious to create the desired stimulus. Look for a requirement that can be easily described in assertions."
Note: For examples of "fun" formal apps dreamt up by Cadence R&D people, see the following:

• Incisive Enterprise Verifier solving Sudoku puzzle in 0.1 seconds
• Incisive Enterprise Verifier driving a Rubik's Cube solving Lego robot

The webinar can be accessed here (quick and free registration required if you're not already a Cadence Community member).
Richard Goering
Related Blog Posts
Video: How Formal Analysis "Apps" Provide New Verification Solutions
DVCon 2012 Video: Product Engineer Chris Komar Reviews the Tutorial on Formal Apps
Archived Webinar: Using Scoreboards With Formal Verification

Using formal “apps” to automate IC verification | LinkedIn

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Functional Verification: Cadence Technical Webinars

Some amount of marketing is inevitable, but I bet there will still be some good stuff here...  :-)

From: Cadence Design Systems <corpmark2@cadence.com>
Date: Wed, Jul 25, 2012 at 5:46 PM
Subject: Advance Your Functional Verification Skills with Cadence Technical Webinars

Advance Your Functional Verification Skills with Cadence Technical Webinars Join Cadence® verification experts for a series of technical webinars on the most relevant topics in functional verification. We'll introduce you to the latest techniques, best practices, methodologies, and support services you need for developing and verifying your silicon designs—productively and profitably! In these concise 1-hour sessions, we'll address hot topics including: SystemVerilog-based debug Better verification performance Power shutoff (PSO) verification Best practices for UVM sequences Implementing multi-language UVM Formal apps to automate verification Combining a metric-driven verification (MDV) flow with an ISO26262 flow TLM 2.0 communication mechanisms and how they are replicated in e Assertion-based verification (ABV) techniques for your ARM®ACE™ implementation You'll get the answers you need to adopt new approaches. You can also follow up with our technical experts, who will set you up with our Incisive® Verification Kit to hone your skills. These webinars are designed to be methodology- and application-based, not a marketing pitch. Plus, you don't need to travel—you can view these presentations and demonstrations from the comfort of your home or office! For more information, or to register: https://www.secure-register.net/cadence/fv_webinars_2h_2012 Application-Specific Webinars (all times below are 9:00 am PT) August 8: Formal Apps to Automate Mainstream Verification Challenges This webinar will show how technology and methodology can be packaged into "apps" that focus on high-value problems that are more efficiently solved using formal-based methods, and can be automated such that very little knowledge of formal or assertion-based verification (ABV) is required… August 21: Why Debug at the Signal Level When SystemVerilog Class-Based Debug is So Simple? This webinar will walk users through the advantages of using the debug power of SimVision within a complex class-based SystemVerilog environment for both interactive and post-process debug... September 11: No More Wrappers – New Interface Between e and SystemC TLM 2.0 Transaction-level models (TLMs) can be used in a number of ways to speed up the design and verification effort for SoCs and their software layers. The last several years has seen strong adoption of SystemC TLM 2.0 for high-level modeling; it has become the de-facto standard for such models… September 18: Is SystemVerilog the Future of Analog Modeling? A significant speed-up in simulation performance can be achieved by replacing the analog portions of a design with functionally equivalent real-number models using real/wreal functionality in Verilog-AMS and/or SystemVerilog to achieve a 100–500x performance boost for top-level SoC verification… September 25: Combining the Best of Both in an MDV Flow – Simulation and Formal There exist many benefits to simulation technology within a metric-driven verification (MDV) flow, and an equal number of benefits using formal technology. Now users can combine these metrics together to take advantage of the best in each… October 16: 5 Steps to Your First Power Shutoff (PSO) Verification Making the leap to your first PSO circuit can be daunting. Do the isolation cells properly insulate the shutoff domain? Do the retention registers enable the SoC to return to full-power properly? Have enough tests been run to cover the power control module?...  October 25: UVM SystemVerilog in a Multi-Language SoC World: UVM-ML While the Accellera Systems Initiative UVM standard is defined for SystemVerilog, its architecture can support multi-language verification environments. Every SoC has some mix of models coded to IEEE and ANSI language standards… November 6: Integrating Chip Verification into an ISO26262 Traceability Flow This webinar will show how to combine a metric-driven verification flow typically used in functional verification with an ISO26262 requirements management flow. The solution entails electronically transferring requirements into the verification flow… November 13: UVM Sequences:  Best Practices for Efficiency and Reuse One of the primary goals of the UVM is to reduce the cost and burden of writing tests. This is accomplished by providing an abstract test definition interface in the form of sequences. Subsequently, much of the complexity involved with driving and monitoring the DUT is absorbed in UVM verification components (UVCs). November 27: SimVision Simplifies UVM SystemVerilog Macro Debug This webinar will introduce the user to the latest in macro debug capabilities offered within the SimVision debug solution. Users of UVM-based environments, where macros are heavily utilized, will find this webinar particularly useful…  December 4: Better Verification Performance – The Ideal Holiday Gift We fight the performance battle all year and growing designs, tests, and test suites constantly make it more difficult. Luckily, Cadence is also constantly developing new capabilities to improve verification performance…  December 11: ACE Assertion-Based Dynamic, Formal, and Metric-Driven Verification Techniques with "ABVIP" To achieve first-pass success, the sophistication of ARM ACE-based designs must be matched by a comprehensive verification approach. This webinar will show how formal and assertion-based verification techniques, combined with assertion-based verification IP (ABVIP), can be used in concert with popular UVM testbench VIP… For more information, or to register: https://www.secure-register.net/cadence/fv_webinars_2h_2012

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Magma Assimilation, Forte (news + jobs), DVcon, Specman e, Atrenta, Calypto

If you care at all about EDA and verification, you should definitely get on John Cooley's mailing list.  Good stuff!

Cheers,
Connie "I Was Assimilated by Cadence, But I Got Better" O'Dell
Sr. Verification Specialist
c.odell@co-consulting.net
303-641-5191
_____________________________________________
CO Consulting - Boulder, CO - http://co-consulting.net

---------- Forwarded message ----------
From: John Cooley
Date: Thu, Mar 8, 2012 at 3:32 AM
Subject: TSMC 28 nm, DVcon, Specman e, Atrenta, Calypto, Forte, SKILL

 "I feel bad for the Magma employees being absorbed by the
  Synopsys Borg.  Today they learn that resistance is futile."

      - An EDA Vendor on SNPS-LAVA merger completing

-------------------------------------------------

 HW forums cite rumor that TSMC suddenly halted 28 nm production
    http://www.deepchip.com/items/0500-01.html

 Brett's quickie trip reports on both DVcon'12 and NASCUG'12 confs
    http://www.deepchip.com/items/0500-02.html

 CDNS too afraid of SV sales to support SNPS/MENT Specman "e"
    http://www.deepchip.com/items/0500-03.html

 Three chip designers hands-on evals of Atrenta Spyglass Power
    http://www.deepchip.com/items/0500-04.html

 We cut another 9% of power using the Calypto RTL PowerPro tool
    http://www.deepchip.com/items/0500-05.html

 Shiv compares IC Manage, CVS, and Subversion for digital design
    http://www.deepchip.com/items/0500-06.html

 I designed a USB 3.0 core using SystemC and Forte Cynthesizer
    http://www.deepchip.com/items/0500-07.html

 Huh? SKILL sklint() already built into the Virtuoso environment
    http://www.deepchip.com/items/0500-08.html

-------------------------------------------------

 Docea Power to unveil AceThermalModeler at upcoming DATE'12
    http://www.deepchip.com/look/see120308-01.html

 Jasper CEO Kathryn Kranen in San Jose Mercury News interview
    http://www.deepchip.com/look/see120308-02.html

 San Jose, CA - Forte seeks SystemC Cynthesizer field engineers
     http://www.deepchip.com/jobs/033.html

Designing, Verifying, and Building an Advanced L2 Cache Subsystem Using SystemC

Forte Design Systems to Demonstrate SystemC High-Level Synthesis at DVCon:

Press Release

At DVCon 2012 Booth #404

Forte Design Systems to Demonstrate SystemC High-Level Synthesis at DVCon

Paneve Paper to Outline its Design Successes Using Cynthesizer

SAN JOSE, CALIF. -- February 20, 2012 --

WHO: Forte Design Systems™, leading provider of software products that enable design at a higher level of abstraction and improve design results

WHAT: Will demonstrate the latest version of Cynthesizer™ SystemC high-level synthesis at DVCon 2012 in Booth #404

WHEN: Tuesday, February 28, from 3:30-6:30 p.m., and Wednesday, February 29, from 4:30-7 p.m.

WHERE: Doubletree Hotel, San Jose, Calif.

Thomas Tessier, vice president of Research and Development at Paneve LLC, will describe Paneve's experiences using Cynthesizer with a paper, "Designing, Verifying, and Building an Advanced L2 Cache Subsystem Using SystemC" at DVCon. It will be presented during Session 3 titled "SystemC and Beyond", to be held Tuesday, February 28, from 9 a.m.-10:30 a.m.

For more details about Forte and Cynthesizer, go to: www.ForteDS.com.

Information on DVCon can be found at: www.dvcon.org.

About Forte Design Systems
Forte Design Systems is a leading provider of software products that enable design at a higher level of abstraction and improve design results. Its innovative synthesis technologies and intellectual property offerings allow design teams creating complex electronic chips and systems to reduce their overall design and verification time. More than half of the top 20 worldwide semiconductor companies use Forte's products in production today for ASIC, SoC and FPGA design. Forte is headquartered in San Jose, Calif., with additional offices in England, Japan, Korea and the United States. For more information, visitwww.ForteDS.com.

Forte acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

For more information, contact:

Brett Cline, Forte Design Systems
(978) 206-1855
brett@ForteDS.com

Nanette Collins, Public Relations for Forte Design Systems
(617) 437-1822
nanette@nvc.com

Forte Design Systems to Demonstrate SystemC High-Level Synthesis at DVCon

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SystemC Users Meeting at DVCon, Agenda

From: NASCUG <Jill_Jacobs@xmr3.com>
Date: Wed, Feb 22, 2012 at 10:25 PM
Subject: SystemC Users Meeting at DVCon

Join Us for NASCUG XVII North American SystemC Users Group at DVCon 2012 Monday, February 27 8:30am - 12:00pm DoubleTree Hotel, San Jose, California www.nascug.org NASCUG provides a unique forum for sharing SystemC™ user experiences among industry, research and universities. NASCUG operates independently but works in collaboration with the Accellera Systems Initiative to provide open forums for promoting information exchange. Our goal is to make SystemC end-users more effective through shared knowledge, user interaction and collaboration. Participation is free. Register now > Agenda 8:30am - 9:00pm Registration 9:00am - 9:10am Welcome, Agenda & NASCUG Introduction Tor Jeremiassen, Texas Instruments, USA 9:10am - 9:25am Accellera Systems Initiative Update Shishpal Rawat, Chairman, Accellera Systems Initiative 9:25am - 9:55am Roundtable: Leveraging Synergy: Future Opportunities with SystemC Moderated by Ed Sperling, System Level Design 9:55am - 10:20am What does C++2011 mean to SystemC? David C Black, Doulos, USA 10:20am - 10:45am Synchronization between a SystemC-based Off-line Restbus Simulator and a Hardware-In-the-Loop FlexRay Network Gilles Bertrand Defo, University Of Paderborn, Germany 10:45am - 10:55am Break 10:55am - 11:20am Extending Fixed Sub-systems at the TLM Level - Experiences from the FPGA World Frank Schirrmeister, Cadence, USA 11:20am - 11:45am A Generic Language for Hardware & Software, Are We There Yet? An Explorative Case Study Examining the Usage of SystemC for Multicore Programming Sushil Menon, University of Pennsylvania, USA 11:45am - 12:00pm Closing Remarks and Prize Drawing Jack Donovan, Duolog, UK 12:00pm - 1:30pm Sponsored Luncheon: Town Hall Lunch with Accellera Systems Initiative View full agenda >   Accellera Systems Initiative Day SystemC, UVM, UCIS, IP-XACT and More Accellera Systems Initiative™ is pleased to announce an exciting program of events for the first ever Accellera Systems Initiative Day on Monday, February 27! Accellera Systems Initiative Day focuses on providing in-depth knowledge for our emerging and established standards to our user community. We are hosting a forum for SystemC users and conducting four tutorials on standards with sessions running concurrently throughout the day. We'll also host an interactive town hall lunch and discuss "What will success for the Accellera Systems Initiative look like?" Agenda 8:30am - 12:00pm North American SystemC Users Group 8:30am - 5:00pm Tutorial: UVM: Ready, Set, Deploy! 12:00pm - 1:30pm Sponsored Luncheon: Town Hall Lunch with Accellera Systems Initiative 1:30pm - 5:00pm Tutorial: An Introduction to IEEE 1666-2011, the New SystemC Standard 1:30pm - 3:00pm Tutorial: An Introduction to the Unified Coverage Interoperability Standard 3:30pm - 6:30pm Tutorial: Verification and Automation Improvement Using IP-XACT Find out more and view agenda matrix >   Global Sponsors Accellera Systems Initiative, 1370 Trancas Street, #163, Napa, CA 94558

MOD Marketing

SystemC/UVM/Verification Learning opportunities at DVCon 2012, San Jose, CA

From: Doulos Training <doulos@email.doulos.com>
Date: Wed, Feb 22, 2012 at 5:02 PM
Subject: Learning opportunities at DVCon 2012

ALL THE LATEST NEWS FROM DOULOS View this email in a web page / Change how you receive emails from Doulos Event news: DVCon 2012 - San Jose, CA Doulos at DVCon (Booth 701): World first tutorial on new standard SystemC User Group meeting SystemVerilog/UVM at DVCon Tutorial on the new SystemC standard Doulos CTO, John Aynsley is organizing the world's first tutorial explaining the features of the new SystemC standard, on Monday February 27, at DVCon 2012 in San Jose next week. This tutorial represents a unique chance to improve your understanding of SystemC as well as giving you a kick start with the new language standard, including the marriage of the SystemC and TLM-2.0 libraries. Full SystemC tutorial session details SystemC training and support The Doulos Guide to SystemC Register for DVCon 2012 Great agenda at NASCUG XVII There are plenty of useful, user-focussed papers and presentations making up the North American SystemC User Group meeting located at DVCon. Doulos specialist, David C Black, will be taking a look at some of the features of C++2011 and illustrate how they could change the way code is written. More details about this meeting on Monday February 27 Other recommended learning opportunities at DVCon 2012 Monday February 27: UVM: Ready, Set, Deploy Tuesday February 28: Easier SystemVerilog with UVM: Taming the Beast Wednesday February 29: Comprehensive Register Description Languages Catch up with the Doulos team at Booth 701 - DVCon floorplan

For more information please call the Doulos team on 1 888 GO DOULOS or email info.usa@doulos.com
Copyright 2012 Doulos Limited. All rights reserved.
Please add doulos@email.doulos.com to your address book


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