What does C++11 mean for SystemC?

	Training Schedule & KnowHow Update
North America: Scheduled Courses Embedded Systems and ARM ESL and SystemC Hardware Design SystemVerilog and UVM Paper and code download: What does C++11 mean for SystemC? In September of 2011, ISO approved an update to the C++ standard, which is known variously as ISO/IEC 14882:2011, C++0x and C++11. This paper by Senior Member of Technical Staff, David C Black, takes a quick look at some of the features and illustrates how they can change the way we write SystemC code for the better. View "What does C++ mean for SystemC?" now The Doulos Guide to SystemC Extended video with download: First Steps with UVM - Part 2 Doulos CTO, John Aynsley, presents a simple, complete SystemVerilog UVM source code example (which you can download), explaining what is happening and highlighting best practice. You are shown how to drive pins on the design-under-test interface from the UVM verification environment, and how to pass a virtual interface using the configuration database. More info: UVM - The Universal Verification Methodology  FREE KnowHow: Latest updates in Doulos KnowHow First Steps with UVM: Part 2 Missed Part 1? Click here

Using formal “apps” to automate IC verification

Webinar Report: How Formal “Apps” Ease IC Verification

By Richard Goering on August 16, 2012Comments(0)Filed under: Industry Insights, IP-XACT, verification, Incisive, IEV, Formal Analysis, IFV, VIP, webinar, assertions, ABV,assertion-based verification, formal verification, properties, code coverage, formal scoreboard, Mueller, Rubik's cube, Lego robot, reachability, Hupcey, formal apps, register map, protocol compliance, SoC connectivity, Sudoku, linting, formal applications, functional verificatioin, ABVIPFormal verification applications, or "apps," can significantly lighten the IC verification workload without requiring a knowledge of assertion-based verification (ABV) - or even, in most cases, the need to write assertions. A recently archived Cadence webinar, held Aug. 8, 2012, describes some helpful formal apps and encourages users to build their own.
The webinar, titled "Formal Apps to Automate Mainstream Verification Challenges," was presented by Joseph Hupcey III, product marketing director at Cadence, and Joerg Mueller, staff solutions engineer at Cadence. It is part of an ongoing series of free functional verification webinars that will run through mid-December.
Hupcey began the webinar by talking about the challenges that have limited the adoption of formal and ABV technologies. He noted that many engineers do not want to learn about assertion languages, that most engineers do not want to learn about formal techniques, and that verification leads have trouble showing the value of formal in the context of a full project. While there's an assumption that it takes a PhD to run formal verification, "that's not true today, and we'll show you a way to automate that away completely," Hupcey said.
What's a Formal App?
In a general sense, Mueller said, an app runs on a platform - in this case, on Cadence Incisive Formal Verifieror Incisive Enterprise Verifier. He offered this three-part definition of a formal app:

• A well-documented tool capability or methodology focused on a specific, high-value problem
• The problem is more efficiently solved using formal methods than using simulation-based methods
• The need to create properties or have ABV knowledge is significantly reduced, because properties can be generated automatically or provided in a pre-packaged form

The webinar then described the formal apps depicted below. As the chart shows, formal apps can be used at different stages of the project life cycle, from early RTL development to system tapeout.

Formal apps across the project life cycle Automatic Formal Analysis and Super Linting
The top two apps identified on the chart work together to provide an advanced linting solution in which properties are generated directly from the implied behavior of the RTL. This is needed because designers generally do not provide adequate verification for the code they write. An HDL analysis linting capability links checks and messages back to the source code. Automatic formal analysis automatically provides checks for such concerns as dead code, finite state machine, pragmas, X states, busses, range overflow, and toggling. HDL analysis linting combined with automatic formal analysis results in "Super Linting."
Protocol Compliance
Protocols are well-defined in written specifications, but what we need to verify against is an executable specification. The solution is to use pre-packaged properties along with assertion-based verification IP (ABVIP) for a given protocol. Cadence now provides ABVIP for major AMBA protocols and for OCP, and it can be used in both simulation and formal verification. Protocol-aware debug, now available in the Cadence SimVision user interface, offers protocol-specific transaction-level debugging. The webinar includes a demo.
Formal Scoreboard
Formal verification has historically been targeted only to control-oriented functionality, but data transport checking is actually a "sweet spot" for formal technology, according to Mueller. The solution is to provide a set of pre-packaged properties that are tuned for data transport checking using sequences of symbols. The basic idea is to force (or constrain) a sequence of input values, and check (assert) that the same sequence appears on the output. Cadence Incisive Formal Verifier and Incisive Enterprise Verifier provide a Formal Scoreboard Template that can help with this task.
Code Coverage Unreachability
This is "probably the fastest growing formal app that we see in the marketplace at the moment," according to Mueller. The problem is that holes in code coverage can take weeks to analyze manually. If you can sort out unreachable (impossible to hit) coverage holes, the task will be easier. This formal app analyzes whether uncovered code is reachable (in which case the test suite is insufficient) or unreachable (solved by fixing RTL or discarding the hole). A demo shows that this process is fully automatic and that users don't even see the formal tool running.
(Note: A user case study of a code coverage unreachability formal app is provided in an archived CDNLive! India 2011 paper by Freescale. )
Register Map Validation
All too often, simulation insufficiently checks for correct register map access and absence of corruption. A formal app can generate properties automatically from an IP-XACT specification, and greatly simplify the register map validation flow. The assertions can check value after reset, register access policies, and the use of write-read sequences with front door and back door access.
SoC Connectivity
This is the oldest and most mature formal app, in production since 2005, Mueller said. It automatically generates properties from the connectivity specification in order to quickly and efficiently verify IP integration. The spec defines internal connections as well as external connections to and from I/O pads. The app provides forms and wizards to ease specification entry and import into a spreadsheet, lets users import results from analysis, and offers built-in connectivity "linting." A demo shows how to edit a spreadsheet, run connectivity checks, debug a failure, and back-annotate results to the spreadsheet.
Dream Your Own!
"What we want to encourage you to do now," Mueller concluded, "is to dream up your own formal apps. Look for verification problems that are boring, repetitive, or inefficient with simulation because it is difficult or tedious to create the desired stimulus. Look for a requirement that can be easily described in assertions."
Note: For examples of "fun" formal apps dreamt up by Cadence R&D people, see the following:

• Incisive Enterprise Verifier solving Sudoku puzzle in 0.1 seconds
• Incisive Enterprise Verifier driving a Rubik's Cube solving Lego robot

The webinar can be accessed here (quick and free registration required if you're not already a Cadence Community member).
Richard Goering
Related Blog Posts
Video: How Formal Analysis "Apps" Provide New Verification Solutions
DVCon 2012 Video: Product Engineer Chris Komar Reviews the Tutorial on Formal Apps
Archived Webinar: Using Scoreboards With Formal Verification

Using formal “apps” to automate IC verification | LinkedIn

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DVClub-Graph Based Verification in a UVM Environment.mp4 - YouTube

DVClub-Graph Based Verification in a UVM Environment.mp4 - YouTube:
Looks interesting; didn't know DVClub posted their presentations as videos on YouTube.  Enjoy!

DVClub-Graph Based Verification in a UVM Environment.mp4

 

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Published on Jul 4, 2012 by Mike Bartley

Staffan Berg, Mentor Graphics
Graph-Based Verification in a UVM Environment

Abstract:
Graph-or Rule-based verification methods is gaining credibility within the verification community that it can provide significantly shorter time-to-coverage than traditional Constrained Random techniques. However, adoption of new methods requires both an understanding of the respective technology and the implications of injecting it into an existing process and infrastructure.

Examples will be presented to illustrate how to write the sets of rules and constraints which Graph-Based verification relies on to define the stimulus space and coverage goals. Coupled with the examples will be assessments of the impact on the resulting number of required simulation cycles.

The second part of the presentation will explain how graph based methods can be introduced to an existing UVM based testbench infrastructure in a non-intrusive way.

Category:

Science & Technology

Tags:

• +computer
 
• +Hardware-Verification

License:

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Functional Verification: Cadence Technical Webinars

Some amount of marketing is inevitable, but I bet there will still be some good stuff here...  :-)

From: Cadence Design Systems <corpmark2@cadence.com>
Date: Wed, Jul 25, 2012 at 5:46 PM
Subject: Advance Your Functional Verification Skills with Cadence Technical Webinars

Advance Your Functional Verification Skills with Cadence Technical Webinars Join Cadence® verification experts for a series of technical webinars on the most relevant topics in functional verification. We'll introduce you to the latest techniques, best practices, methodologies, and support services you need for developing and verifying your silicon designs—productively and profitably! In these concise 1-hour sessions, we'll address hot topics including: SystemVerilog-based debug Better verification performance Power shutoff (PSO) verification Best practices for UVM sequences Implementing multi-language UVM Formal apps to automate verification Combining a metric-driven verification (MDV) flow with an ISO26262 flow TLM 2.0 communication mechanisms and how they are replicated in e Assertion-based verification (ABV) techniques for your ARM®ACE™ implementation You'll get the answers you need to adopt new approaches. You can also follow up with our technical experts, who will set you up with our Incisive® Verification Kit to hone your skills. These webinars are designed to be methodology- and application-based, not a marketing pitch. Plus, you don't need to travel—you can view these presentations and demonstrations from the comfort of your home or office! For more information, or to register: https://www.secure-register.net/cadence/fv_webinars_2h_2012 Application-Specific Webinars (all times below are 9:00 am PT) August 8: Formal Apps to Automate Mainstream Verification Challenges This webinar will show how technology and methodology can be packaged into "apps" that focus on high-value problems that are more efficiently solved using formal-based methods, and can be automated such that very little knowledge of formal or assertion-based verification (ABV) is required… August 21: Why Debug at the Signal Level When SystemVerilog Class-Based Debug is So Simple? This webinar will walk users through the advantages of using the debug power of SimVision within a complex class-based SystemVerilog environment for both interactive and post-process debug... September 11: No More Wrappers – New Interface Between e and SystemC TLM 2.0 Transaction-level models (TLMs) can be used in a number of ways to speed up the design and verification effort for SoCs and their software layers. The last several years has seen strong adoption of SystemC TLM 2.0 for high-level modeling; it has become the de-facto standard for such models… September 18: Is SystemVerilog the Future of Analog Modeling? A significant speed-up in simulation performance can be achieved by replacing the analog portions of a design with functionally equivalent real-number models using real/wreal functionality in Verilog-AMS and/or SystemVerilog to achieve a 100–500x performance boost for top-level SoC verification… September 25: Combining the Best of Both in an MDV Flow – Simulation and Formal There exist many benefits to simulation technology within a metric-driven verification (MDV) flow, and an equal number of benefits using formal technology. Now users can combine these metrics together to take advantage of the best in each… October 16: 5 Steps to Your First Power Shutoff (PSO) Verification Making the leap to your first PSO circuit can be daunting. Do the isolation cells properly insulate the shutoff domain? Do the retention registers enable the SoC to return to full-power properly? Have enough tests been run to cover the power control module?...  October 25: UVM SystemVerilog in a Multi-Language SoC World: UVM-ML While the Accellera Systems Initiative UVM standard is defined for SystemVerilog, its architecture can support multi-language verification environments. Every SoC has some mix of models coded to IEEE and ANSI language standards… November 6: Integrating Chip Verification into an ISO26262 Traceability Flow This webinar will show how to combine a metric-driven verification flow typically used in functional verification with an ISO26262 requirements management flow. The solution entails electronically transferring requirements into the verification flow… November 13: UVM Sequences:  Best Practices for Efficiency and Reuse One of the primary goals of the UVM is to reduce the cost and burden of writing tests. This is accomplished by providing an abstract test definition interface in the form of sequences. Subsequently, much of the complexity involved with driving and monitoring the DUT is absorbed in UVM verification components (UVCs). November 27: SimVision Simplifies UVM SystemVerilog Macro Debug This webinar will introduce the user to the latest in macro debug capabilities offered within the SimVision debug solution. Users of UVM-based environments, where macros are heavily utilized, will find this webinar particularly useful…  December 4: Better Verification Performance – The Ideal Holiday Gift We fight the performance battle all year and growing designs, tests, and test suites constantly make it more difficult. Luckily, Cadence is also constantly developing new capabilities to improve verification performance…  December 11: ACE Assertion-Based Dynamic, Formal, and Metric-Driven Verification Techniques with "ABVIP" To achieve first-pass success, the sophistication of ARM ACE-based designs must be matched by a comprehensive verification approach. This webinar will show how formal and assertion-based verification techniques, combined with assertion-based verification IP (ABVIP), can be used in concert with popular UVM testbench VIP… For more information, or to register: https://www.secure-register.net/cadence/fv_webinars_2h_2012

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First Steps with UVM - Part 1, Courtesy of Doulos

New! Extended Video with Download: First Steps with UVM - Part 1

Doulos CTO, John Aynsley, presents a simple, complete UVM source code example (which you can download), explaining what is happening and highlighting best practice. You are shown how UVM source code is organized and how to run the example on popular SystemVerilog simulators. More info: UVM - The Universal Verification Methodology

First Steps with UVM: Part 1

From:
http://www.doulos.com/content/email/1206_ScheduleNA.html

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First Steps with UVM Part 1 - YouTube

First Steps with UVM Part 1 - YouTube:

Published on May 14, 2012 by aijnsleij

John Aynsley from Doulos presents a simple, complete UVM source code example (which you can download), explaining what is happening and highlighting best practice. You are shown how UVM source code is organized and how to run the example on popular SystemVerilog simulators.

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DVClub April 2012 on Adopting UVM | TVS

DVClub April 2012 on Adopting UVM | TVS:

Follow Mike

DVClub discusses adoption of UVM

The DVClub event on 23rd April 2012 focused on “Adopting UVM”. There were 3 talks
Easier UVM – Functional Verification for Mainstream Designers by John Aynsley, Doulos.
Essentials for Developing and Deploying SV-based VIP – Manish Tanwar, Senior Verification Engineer, TVS, Bangalore, India
The UVM Register Layer, Introduction and Experiences by Steve Holloway – Senior Verification Engineer, Dialog Semiconductor, UK

Follow the link to get access to slides and recordings of the presentations
Join LinkedIn Group “DVClub Bristol” to be kept informed of events

DVClub April 2012 on Adopting UVM testandverification.com

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4 days ago

Design verification, etc., instructional videos from the Doulos Video Gallery

Nice selection of videos, check it out!
I looked at the 2012 DVCon videos on YouTube so far, but it seems kinda Cadence-centric so far.
Like to see more diversity, but maybe they did not record as much video at DVCon this year as past years.  Too bad.  :-)

Video Gallery :

Video Gallery

We have collected together videos from across the site in this gallery. Enjoy!

Topics covered so far:

VHDL

• What's New with VHDL
• NEW VHDL versus SystemVerilog

SystemVerilog

• Making Sense of Transaction Level Modeling in OVM
• Observation in VMM and OVM
• Ten Things You Should Know About OVM
• Using OVM within SystemC for Verification
• Introducing VMM 1.2
• Introduction to UVM - The Universal Verification Methodology
• SystemC versus SystemVerilog
• SystemVerilog as the New Verilog
• NEW VHDL versus SystemVerilog
• NEW How Much SystemVerilog Training Do You Need?
• NEW SystemVerilog for Hardware Synthesis

SystemC TLM-2.0

• SystemC versus SystemVerilog
• What is TLM-2.0?
• TLM-2.0 Interoperability
• RTL vs TLM and AT vs LT
• TLM-2.0 Protocol Checker

ARM Cortex

• ARM Cortex-M1 for FPGAs
• Introduction to CMSIS for ARM Cortex-M
• Using the Cortex-M3/M4 Flash Patch Breakpoint Unit
• Using your C Compiler to Exploit NEON

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