Costello ("3 Big Dogs...") on Startup Story Telling, thanks to Paul McLellan (Hi, Paul!) and SemiWiki

I still remember Joe Costello describing EDA as "3 big dogs around 1 tiny bowl of dog food" (after Cadence acquired BLDA). I decided he was right - it is why I am now in a design house instead of EDA! - Cheers, Connie

Costello on Story Telling

by

Paul McLellan

Published on 05-02-2013 08:03 PM

0 Comments 

Last night at Cadence was the next installment of what I have been calling Hogan University. Jim interviewed Joe Costello about how to tell a story as part of the EDAC emerging companies series of events. The main focus was how to tell a story as a small EDA company communicating with investors, although there are obviously other forms of communication. I'm assuming that if you are reading SemiWiki that you know that Joe Costello was CEO of Cadence for many years, taking it from its birth as a merger of ECAD and SDA to a big EDA company (I think over $1B by the time he left).

Rather like in his keynote at DAC a few years ago, Joe tried to distill things down into some rules (some of them the same rules even).

So rule #1, if you want to tell a compelling story then you have to have a compelling story. You can mess up a good story by the way you tell it, but you can't make a poor idea good by the way you tell it. The biggest failure in pitching to investors is not how you tell it, it is just that your story is not compelling. "The common cold is interesting but smallpox is compelling."

Rule #2, which also was one of the keynote rules and clearly everyone who worked for Joe had already heard: write the press release first. It will never sound better when it is just a dream and you haven't had to make any compromises in implementation. So if it doesn't sound good as a press release then...maybe time to think again ("pivot" in current VC terminology).

Rule #3 is to look at things from the point of view of the investors you are pitching to. This is a bit like the "think like a fish" rule at Joe's keynote that had him lying on the stage pretending to be a fish. You might want to create a company to change the world, or to experience a startup, or to follow your dreams. Investors mostly want to make money, but they also have other agendas (like looking good to their partners or expanding into whatever all the other VCs are investing in that week). Yes, they want to see passion, but mostly because passion means you are more likely to make the effort necessary to succeed.

Rule #4 is to be yourself, don't try and imitate Steve Jobs (or Joe Costello) in the way you present. You have to own your story and do it the way you want. Oh, and don't use slides except for a few pictures/graphs. Joe didn't mention it but there is actually a lot of research that shows that if your slides are basically bullet points that tell the whole story then they detract, not add, to your presentation. Just use slides to add graphics and emotion to what you are saying (watch any Jobs keynote to see the master at work, no bullet points to be seen). Or don't use them at all.

Rule #5 is that you need to get to the emotional needs of whoever you are pitching to. Break up logical thinking with humor, oddball facts and tangential stuff. And no slides with bullet points (see above).

Here is an interesting point I'd never heard before. Intel pays more to PG&E for simulation than it pays the entire EDA industry for all the simulators they use. And they don't even bitch about electricity prices.

When Joe left Cadence, apparently he interviewed with Jobs to be CEO of Apple. Steve eventually said that he only had experience selling very geeky stuff to very geeky companies. He had no experience selling to consumers. Joe tried to point out that every developer is a human being and has to be sold to. I guess Jobs wasn't convinced since Joe didn't get the job.

With that, it was time for us all to go home.

SemiWiki - Costello on Story Telling

'via Blog this'

EDA Mergers and Acquisitions Wiki - SemiWiki

Cool!  Accurate as far as I can tell, being a former member of Bell Labs Design Automation:

EDA Mergers and Acquisitions Wiki 

• Rate This Page

A Compilation of EDA Company Merger Listing All the Logos an EDA Company Owns
This list is a compilation over many years of mergers and acquisitions in the EDA market. The original compilation was done by an individual (Ian Getreu [1]) and is not an official list associated with any company or organization. Companies that have not bought or merged with other companies are not included in the list.

There is no guarantee of accuracy or completeness. Mergers and acquisitions that were not announced via press releases are probably not included. We welcome any additions and corrections.

The original objective was simply to list the number of logos owned by a company. So, if company A bought company B and was then bought by company C, this would be listed via indentations as:

Company C

Company A

Company B

(****SO**** means a Spin-Out)

Blog Article

ADELANTE TECHNOLOGIES

Philips Semiconductor DSP Division
Frontier Design

AGILENT (SO from HP in 1999)

EEsof (Acquired by HP in 1993, Touchstone product)
Alphabit (Momentum)
Eagleware (Genesys)

Elanix (SystemVue)

Xpedion Design Systems (July 28, 2006 - Terms not disclosed. GoldenGate RF IC simulation and analysis.)
Accelicon (December 1, 2011 - Terms not disclosed. 30 people. SPICE model analysis for model quality assurance.)

ALDEC

ALTERA

Right Track CAD

ALTIUM

NeuroCad Inc.
Logical Devices
INCASES Engineering GmbH
Protel International

Accolade Design Automation
MicroCode Engineering
Accel Technologies

Bought P-CAD and the Altium name from IBM 

IBM

(IBM sold mechanical CADAM to Dassault Systemes)
Changed name from CADAM to Altium
Microcadam
IBM CAD
P-CAD

Prance

After IBM sold its mechanical CADAM mainframe and workstation business to Dassault Systemes, the company changed its name from CADAM, Inc to Altium in order to avoid confusion with the product name CADAM. The remaining parts of the firm were Microcadam, IBM CAD, P-CAD and a joint venture in Japan. After the mechanical businesses split off, IBM sold Altium to Accel Technologies in 1995. Protel International acquired Accel in 2000 and in 2001 changed its name to Altium Limited

Green Mountain Design Automation
ICS Interactive (Innovative CAD Software)
Metamor Software
Tasking BV

Morfik Technology 

ANSYS

Ansoft (Acquired in 2008)

MacNeal-Schwendler Corp. (Electronics Business Unit)
Compact Software Inc.
Boulder Microwave Technologies
Pacific Numerix Inc.
Agilent's High Frequency Structure Simulator (HFSS)

Apache Design Solutions (Acquired June 29, 2011 for $310 Million in cash)

NSPICE
Baynacre
Optimal Corp
Sequence Design (Acquired September 8, 2009)

Frequency Technology
Sente Technology
nPower
Sapphire Design Automation

Posedge Inc

ARC INTERNATIONAL PLC

ARC Cores

Tenison Technology EDA Ltd.
MetaWare

ARM

Axys Design Automation
Artisan Components (renamed from VLSI Libraries)

Mentor Graphics' Physical Product Line
Synopsys Physical Libraries Business
NurLogic design

Obsidian Software (17 June 2011)
Prolific Inc. - IC design optimization tools: ProGenesis, ProTiming, ProPower, ProDFMOptimizer. Founded in 1995 by Dr. Paul de Dood. Acquired November 1, 2011, terms not disclosed.

ASIC ALLIANCE

CadWorx Consulting

ASML Holding NV (with these acquisitions ASML is now also in the EDA world)

Brion Technologies Inc.
Masktools Inc.

ASPEC

Verilux Design Technology Inc
Chip & Chip Technologies Inc
Novo Systems Corp (formerly Zycad TSSI)
inBox

ATRENTA

AXIOM Design Automation

New name for @HDL
NextOp Software Inc. (assertion synthesis, June 20, 2012 - terms not disclosed)

AZINI CAPITAL

OneSpin Solutions - formal assertion-based verification tools. January 24, 2011.

BARCELONA DESIGN, INC (Out of business in March 2005. Spent $44M in venture capital, had Joe Costello as Board Member. Similar Analog IP technology as Sabio Labs, now part of Magma.)

CADENCE

SDA (Solomon Design Automation)
ECAD (Dracula)

PDS (Phoenix Data Systems)
Simon (Simulator)

Tangent Systems (Layout)
Sedco (Schematic-symbol generation)
Pinebush Technologies
Gateway (Verilog)

XCAT

ASI (PCB Layout)
UniCAD
Helios (Thermal tool)
Seed VHDL Environment (VHDL simulator - Leapfrog)
Alta Group (ESDA)

Comdisco (ESDA) ------à SPW product line to CoWare

ST*AR (BONES network simulator)

Redwood (ESDA)
Synthesia (Synthesis)

Systems & Networks Inc (Sales arm for Comdisco tools)
Spectrum Services (Consulting)
Advanced Microelectronics (Consulting)
Columbia Design Center (Consulting)
Unisys (STO) (Consulting - ASIC)
HLD (IC Floor Planning)
Cooper & Chyan Technologies (PCB Layout) (1997, $418M, CEO interview)

UniCAD (Layout)

Valid

ADT (Analog Tools)
GE (the division of GE that bought Calma)

Calma (Bought Comsat's simulator business)

Comsat (Bought Tegas)

CCSS (Tegas Logic Simulator)

Tegas Inc (Tegas Support) 

***SO*** IMS (Test)

Telesis (Test and simulation)
Parsec (Timing analysis)
Intermetrics (VHDL test suite)

Wyoming (?)
Synthesia (RTL Synthesis)
Symbionics Ltd. (Design consultants)
Excellent Design Inc (Design consultants)
EXD Technologies Inc. (Design consultants)
Esperan (EDA Training)
Detente (Software Development)
Ambit Design Systems (Synthesis) (1998, $260M)
Bell Labs Design Automation (Simulation, Verification)
Quickturn (Emulation)

SpeedSim
Arkos Div of Synopsys
PIE Design Systems
Mitsui Bussan Digital's emulation business

Design Acceleration Inc (DAI) (Simulation)
***SO*** Alchemy (Design consulting)
***SO*** Accent (Design services)
Orcad (PCB Design)

EDA Bridge from T.E.A.M
Q Point Technology (CIS features)
Microsim (Analog simulation - PSPICE)
Intelligent Systems (Japan Distribution)
Massteck Ltd. (PCB Layout)
ARS Microsystems (UK Distribution)

Diablo Research Company LLC (Design consultants)

***SO*** Tality (Design consulting)
***SO*** SpinCircuit (brought back in)

------->SpinCircuit (Design Services)

Westport Technologies (Design Services - Telecom)
CadMOS (Signal Integrity)

Apres Technologies (assets)

Silicon Perspective Corp (Vitual Prototyping)

Plato Design Systems (IC Router)
Simplex Solutions (Verification)

Snaketech
Altius Solutions Inc
Coyote Systems IP assets from Coventor Inc.

IBM's Design-for-Test Tools Business
Antrim Design Systems assets
Celestry

Ultima Technology
BTA Technology

Get2Chip

Meropa (renamed as Get2Chip)

K2 technologies Inc. (acquired May 7, 2003 - terms not disclosed. Products: K2-MaskCompose, K2-Chameleon, K2-QuickView. Technology came from TI.)
Verplex Systems (acquired July 16, 2003 - terms not disclosed. Products: Conformal LEC logic equivalence checker, Conformal LTX logic transistor extractor, Conformal FPGA equivalence checker, Conformal LVR layout versus RTL, Conformal MEM memory equivalence checker, Conformal Datapath circuitry checker, and BlackTie.)
Q Design Automation (Process migration)
Neolinear (AMS & RF)
Verisity (Test, was named InSpec)

SureFire Verification Inc. (was named Silicon Sorcery)
Axis Systems

Praesegus Inc (DFM)
CommandCAD (DFM)
Invarium Inc (Pattern synthesis)
Clear Shape Technology (DFM)

Chip Estimate Corp (IC planning and IP reuse)

Beach Solutions

VCX Software Limited

Knowlent assets
Nascentric (FastSPICE circuit simulator called AuSIM, parallel simulation, GPU-powered version. Acquired by Cadence in 2009, terms not disclosed)
Taray (FPGA)
Denali (Memory IP, acquired May 2010)
Altos Design Automation (Library Characterization, Press Release: May 10, 2011)
eTop Design Automation (Masco Physical Verifier, became known as PVS, Acquired in 2004)
***SO*** ProPlus (people came from Celestry. Analog simulation)
Azuro (Clock Concurrent Optimization, Press Release: July 12, 2011, amount not disclosed)
SIGRITY (Announced July 2, 2012. Signal and Power integrity analysis. $80M deal.)

Encore Technology (from Synopsys)

CALYPTO

Catapult C (Spin out from Mentor Graphics, August 26, 2011, amount not disclosed)

CARBON

Axys (from ARM)

CAST

Lineage Systems Inc

C LEVEL DESIGN (renamed from Compilogic)

Transmodeling Inc

CLK DESIGN AUTOMATION

Synchronous Design Automation

CYNERGY SYSTEM DESIGN

CAE Plus

DANIHER

Tektronix

TDA Systems

DASSAULT SYSTEMS

MatrixOne

Synchronicity Software
IPinfraNET product from Cadence

Elsys (electrical PLM, Products: electre, catelectre, smartelectre. October 26th, 2011 - terms not disclosed.)

DOULOG

Beach Solutions

ELECTRONIC WORKBENCH

Interactive Image Technologies (rename)
Ultimate Technologies

EMA DESIGN AUTOMATION

Chronology Division from Forte Design Automation
Design Advance

ENTROPIC

Vativ

ESSENSIUM NV

Mind NV

EVE

Tharas Systems

EXPRESSIVE SYSTEMS INC

Vizef

FORTE DESIGN AUTOMATION

Chronology Inc à EMA Design Automation
CynApps (was named C2 Design Automation)
Arithmatica

GATEFIELD (renamed from Zycad, August 1997)

Zycad

Integrated circuit Applications (InCA)
Silicon Solutions

sold fault-acceleration to Ikos Systems 

Attest Software Inc.

ExperTest sold fault-simulation to Credence/TSSI, sold to Aspec

GENEDAX

Expressive Systems Inc.

GENNUM CORP

Snowbush Electronics 

HELLMAN & FRIEDMAN, TEXAS PACIFIC GROUP

Intergraph

HP-MICROWAVE

HP

Eesof
Optimization Systems Associates Inc.

ICERA

Sirific Wireless

INTEL

Wind River

Virtutech

CoFluent Design (CoFluent Studio EDA, acquired September 13, 2011, amount undisclosed, founded in 2003).

INTERCEPT

Harris EDA's PC Board tools

JASPER DESIGN AUTOMATION

Safelogic

JAVELIN DESIGN AUTOMATION

Icinergy Software (assets)

JUNIPER NETWORKS

Micro Magic Inc.

------ Spun back out

KEY ASIC (new name for Arcadia)

ARCADIA DESIGN SYSTEMS

SiliconX

MacNEAL-SCHWENDLER

MacNeal-Schwendler

Automotive Analytics

MEMSCAP

Cronos Integrated Microsystems Inc

Mentor Graphics

CADI (Board Layout)
Caedent (Logic Simulator)
Contour/Acotech (Analog Libraries)
Synergy Dataworks (Hardware accelerator)
Context (Documentation)
Trimeter (Synthesis)
Tektronix CAE (CAE)

VR Info Systems (Standard Cell Layout)
CAE Systems (CAE)

Tektronix CASE (CASE)
Performance CAD (Timing analyzer)
Parade (Small FPGLA)
Checklogic (ATPG)
Silicon Compiler Systems (SCS)

Silicon Design Labs (Generator Development Tools, Lsim)
SCI (Silicon Compilers Inc - Genesil)

Caeco (CAE)
Descartes (P&R)
EDC (Silvar-Lisco's European R&D)
TI (CheckMate - LVS, MaskPE - LPE)

Anacad (Analog simulation)

EES (Analog simulation)
Egypt Model Technology (Analog modeling)

Axiom Daterer Skandinavien (Schematic-symbol generation)
Meta-Systems (Logic emulation)
Microtec Research (Embedded systems)

Hunter & Ready (Real-time OS software)
ONE (Network management tool)

Precedence (Backplane)
Zeelan Technology (Signal Integrity Models)
----------------> Z2 Consulting LLC (SO)

Integrity Engineering (Signal Integrity Simulation)
3Soft (Digital models)
CoSoft (PC Schematic Entry)

SETO Software GmbH (PCB layout)
Interconnectix (Interconnection synthesis)
Royal Digital Centers Inc (PCB - manufacturing links)
dQdt (DSP function blocks)
Systolic Technology Ltd. (Telecomm blocks)
Open Networks Engineering (Telecomm blocks)
CAE Technology Inc. (Peripheral controllers blocks)
CLK Computer-Aided Design Inc. (Timing-driven placement & optimization)
OPC Technology (Optical proximity correction software)
Veribest (part of Intergraph)

M&S Computing
DAZIX

Daisy Systems
Cadnetix
HHB
Shiva

Vizef

---------------> Physical Library Division to Virage Logic
Escalade (ASIC HDL graphical design tools)
Descon Informationssysteme GmbH (Product Data Management)
HLS (High-level synthesis)
CADIX ECAD Division (Printed Circuit Board)
Antares 

Model Technology (VHDL Simulator)
Exemplar (Digital Synthesis)
Harness Software Group (Harness Software)
SpeedGate Design Automation (Emulation)
Capital H (Wire Harness)
Accelerated Technology (RTOS)
Ikos (Hardware Emulation)

Racal Redac (VHDL Simulator)
Virtual Machines
Zycad (Emulator, August 1997)

Interra

Delsoft (India)

Deerbrook Systems

Innoveda (Systems)

Summit ---------------------------> Summit Design

TSSI -------------------> Credence
SEE Technologies
TriQuest Design Automation
Simulation Technologies

Viewlogic

Transcendent Design Technology

PADS Software

HyperLynx
ACT (Advanced CAM Technologies)

Assets of DDE-EDA A/S, (PCB packaging)
Alcatel's Ethernet & MAC IP business (IP)
FirstEarth (Wiring)
Project Technology (UML tools)
0-in Design Automation (Verification)
Atair GmbH (Compiler)
Palmchip Parallel & Serial ATA IP business (IP)
EverCAD Software (Fast SPICE simulator)
Volcano Communications Technologies (Automotive network design tools)
Aptix (Emulation)

--------------------------------------- Cre8Ventures (UK company supporting users)

Summit Design (ESL)
SpiraTech Ltd (ESL)
Sierra Design Automation (Place & Route)
NXP Semiconductor DFT tools and people
Assets of Ponte Solutions Inc (DFM)
Flomerics Group (Thermal analysis)
C Synthesis assets of Agility Design Solutions

Catalytic (name change)
Celoxica Holdings ESL business

Logicvision

SiVerion

Embedded Alley Solutions
Valor Computerized Systems (PCB)
Zeland (3D field solver)
Virtual Garage (from Freescale) (Automotive tradeoffs)
Valor Computerized Systems Ltd (PCB)
Pextra (3D Field Simulation, acquired in 2010?)
Pyxis (Custom IC routing, acquired Q3 2010)
CodeSourcery Inc assets (Open-source tool chains for system development, acquired Dec 10 , 2010)
Flowmaster Group (computational fluid dynamics simulation software, terms not disclosed, announced January 9, 2012)

METHODICS

Missing Link Tools (EVOLVE - Agile framework for build, test, regressions. Terms not disclosed. May 31, 2012)

MICROCOSM TECHNOLOGIES

Coyote Systems

MICRO MAGIC

(Spun back out from Juniper)

MINC

Futurenet
ENDOT
Synario

MIPS TECHNOLOGIES

Chipidea Microelectronics SA

NATIONAL INSTRUMENTS

Electronics Workbench
AWR (High frequency tools, $58M, Announced on May 23, 2011)

Accolade from I/Q Com Corp
--------------> SO as Visual System Simulator
APLAC

OPEN-SILICON INC

Zenasis Technology IP assets (Zenasis folds)

PARAMETRIC TECHNOLOGY CORPORATION

OHIO Design Automation Inc

PDF SOLUTIONS

IDS Software Systems
WAMA Technology from WaferYield Inc
Si Automation SA
Fabbrix Inc

POLICYONE

Duet Technologies (was named Software & Technologies)

CrossCheck Technology

Aida (from Teradyne EDA)

Cascade Design

TunnelNet

PRECIENCE

Technology Solutions Inc (Pakistan)

QUALCORE LOGIC

LEDA Systems Inc.

QUALCOMM

Rapid Bridge (LiquidCell Library, announced June 13, 2011. Terms not disclosed.)

SAGANTEC

NP-Komplete Technologies (May 3, 2012 - terms not disclosed)

SEVA TECHNOLOGIES

Intrinsix Inc

SILICON AND SOFTWARE SYSTEMS (S3)

Acacia Semiconductor SA

SILICON VALLEY RESEARCH (SVR)

Silvar Lisco
Quality I.C.

SILVACO

Simucad (Spin-out from Silvaco in June 2004, merged back into Silvaco, Inc. in March 2010)

Space Codesign

SynaptiCAD

Right to sell ASC tools

Synopsys

OSI (spin-out from GE)
Zycad's simulator

(Data I/O
Futurenet
ENDOT)

Compiled Designs
SC High Tech (Japanese distributor)
Cadis
Logic Modeling

LAI
LMC
LMSI
Silicon West

Quadtree

Arcad
Silicon Architects
Arkos Design
Excelsior Research (investment, not purchase)
Epic Design Technology

Archer Systems
Cida

VLSI Libraries (10% stake, not ownership)
(Viewlogic)

Vantage
Abstract????
Racal-Redac parts
Quad Design
Sunrise Test

ExperTest

Chronologic Simulation
Silerity
EDAS Europe BV, The CAE Co. BV
Transfer Electronic Design Support
Eagle Design Automation

Radiant Systems
Everest Design Automation
CoverMeter
Smartech Oy
Gambit Automated Design
Apteq
Stanza
Systems Science
VirSim
TSG
LEDA S.A.
The Silicon Group
C Level Design Inc assets (not the company)
Avant!

Arcsys + ISS (Merger announced August 22, 1995 forming Avant!)

Psi

Anagram
Meta-Software (HSPICE)

MasterToolBox company

Frontline Design Automation
Nexsyn
--------------------> AvanWise
Compass

CLSI Solutions

--------------------> Galax!
Technology Modeling Associates (TMA)

Precim

Datalink Far East Ltd.
Arcus Technology
ACEO Technology
interHDL
Xynetics Design Systems

Harris EDA (rename)

Chrysalis Symbolic Design
Analogy

Symmetry Design

inSilicon

Xentec
Phoenix Technologies (spun out InSilicon)

Sand Microelectronics
Virtual Chips

RAVIcad (renamed as Virtual Chips)

Co-Design Automation
Numerical Technologies Inc.

Transcription Enterprises Ltd.
Cadabra Design Automation

Qualis verification IP assets
Innologic Systems Inc.
Analog Design Automation
Accelerant Networks
Memory BIST Division of iRoC Technologies
Integrated Systems Engineering (ISE)
Monterey Design Systems (assets)

Aristo Technology

Cascade Semiconductor Solutions (also known as Cascade IP)
LEDA Design (assets)
Nassda
The staff of Zeta Infotech
HPL Technologies

----------------- Encore technology (sold to Sigrity)

Virtio
Sigma-C AG
ArchPro Design Automation
MOSAID Semiconductor IP assets
Sandwork Design Inc
Synplicity

Iota Technology Inc signal integrity & power analysis technology
Bridges2Silicon Inc.
HARDI Electronics AB

ProDesign’s CHIPit Business Unit
MIPS Technologies Analog Business Group

ChipIdea Microelectronica SA

VaST Systems Technology Corporation (Announced Feb 2, 2010, terms not disclosed)
Gemini Design Automation (GSim - a SPICE circuit simulator. Reported March 11, 2010. Terms not disclosed. Founded in 2005.)
CoWare Inc (announced Feb 8, 2010, terms not disclosed)

Comdisco SPW product line (from Cadence)
LisaTek Inc

Virage Logic Corp (Announced June 10, 2010 for $315 million. Semiconductor IP.)

Mentor Graphic's Physical Library Division
Impinj NVM IP business

NuSym Technology (Announced June 28, 2010. Terms not disclosed. Intelligent testbench technlogy.)
NXP Semiconductor IP
Synfora assets

Esterel Studio from Esterel EDA Technologies (France)

Optical Research Associates

nSys (Verification IP, September 2, 2011, price not disclosed)

Extreme DA (Acquired October 6, 2011, terms not disclosed. Statistical Static Timing Analyzer - GoldTime)

Xigmix

MAGMA DESIGN AUTOMATION (Acquired November 30, 2011. Priced at $507M or $7.35 per share.)

Moscape
Aplus Design Technologies
Silicon Metrics (2003, $32M, Press Release, Press Release)
Random Logic (2003, $25M, Press Release)
Mojave Design
VeraTest
PDAT
ReShape (assets)
ACAD
Knights Technology (from FEI)
Rio Design Automation
Sabio Labs

ExpertIO (Announced January 23, 2012. Verification IP. Terms not disclosed.)
Inventure (Announced January 24, 2012. A subsidiary of Zuken, Japan. Interface IP. Terms not disclosed.)
RSoft Design Group (Announced May 9, 2012. Photonics design and simulation software. Terms not disclosed.)
Ciranova (Announced July 30, 2012. Analog IC layout automation tools: Helix, PyCell, Pyros Viewer. Terms not disclosed. Blog by Daniel Payne.)
SPRINGSOFT INC (Announced August 3, 2012. $305M cash deal. Blogs by Daniel Payne, Paul.)

Novas Software
Silicon Canvas
Fortelink
Novaflow
Nanovata

Certess

TELA INNOVATIONS INC

BLAZE DFM 

Aprio

TNI-VALIOSYS SA

Arexsys SA
Techniques Nouvelle d'Informatique SA (TNI)
TransEDA

DualSoft
iModl Inc

TransEDA SYSTEMS

Sold by Valiosys

TANNER

Tanner EDA

TEKTRONIX

Veridae (ASIC/FPGA prototyping, announced July 5, 2011. Terms not disclosed.)

TERADYNE EDA

Aida (ATPG, HW & SW simulation, STA)
Case Technology (Schematic capture, PCB layout, simulation)

VIGILANT SYSTEMS

EDAConnect

Javelin EDA

VALIOSYS

TransEDA

VERIGY

Credence

Fluence Technology

TSSI
xxx (California company)
xxx (California company)
Opmaxx

Tektronix's Test Business

New Millenia Solutions Inc
Integrated Measurement Solutions
NPTest

LTX

XILINX

Neocad
Visual Software Solutions & formal-verification technology from Veriphia
Hier Design
AccelChip

Bit-tru

MINC

IST

AutoESL Design Technologies - High level synthesis tools, acquired January 31, 2011

XtremeEDA Corp

ESLX Inc

ZUKEN-REDAC

Zuken
Racal-Redac

Racal
Redac

Thom6
Silc
HHB

Simucad
Shiva

Incases Engineering GmbH

INCASES North America Inc.

CIM-Team GmbH

ZYCAD

Silicon Solutions

[hide] - [top]Footnotes

^ Ian Getreu, IG Associates,(503) 888-2372

inShare0

Contributors: dcblack  , garydpdx  , Colin Warwick  , Daniel Nenni  , Ian Getreu  , John Busco  , Staf_Verhaegen  , daniel_payne

Created by daniel_payne  , 01-16-2011 at 09:17 PM Last edited by daniel_payne  , 08-03-2012 at 01:04 PM Last comment by bee07  on 08-22-2012 at 11:55 PM 25 Comments, 14,362 Views

EDA Mergers and Acquisitions Wiki - SemiWiki

'via Blog this'

Video tutorial: UVM, Ready, Set, Deploy, thanks to Accellera

Home - Accellera Systems Initiative:

http://www.accellera.org/news/videos/uvmreadysetdeploy

New Video Tutorial – UVM: Ready, Set, Deploy!

It’s been six months since Accellera and the Open SystemC Initiative joined forces to become Accellera Systems Initiative. In that time, we have achieved several milestones in developing standards that address the real needs of system and semiconductor designers.

The Universal Verification Methodology (UVM) standard continues to gain adoption across the verification community. Presented by expert verification methodology architects and engineers at DVCon 2012, the eight-part video tutorial is available at no cost to users and provides an introduction to key UVM concepts and best practices.

See us at the Design Automation Conference, June 4-7 in San Francisco! We will be hosting several events at this year's DAC including a luncheon on the Unified Coverage Interoperability Standard (UCIS), NASCUG meeting, and special birds-of-a-feather sessions. At the luncheon, Accellera Systems Initiative will receive the Tenzing Norgay Award, and will present its 2012 Leadership Award. Events are no charge with advance registration required. Read the latest article on UCIS featured in our newsletter.

Dennis Brophy Receives 2012 Accellera Systems Initiative Leadership Award 

To be presented at our luncheon at DAC in San Francisco on Wednesday, June 6, 2012

Details >>>

DAC 2012

June 6 | San Francisco, CA

• Hosted Luncheon and UCIS Technical Presentation
• Birds-of-a-Feather Meetings
• NASCUG XVIII

Find out more >

SystemC Japan

July 6 | Yokohama, Japan

DVCon 2013

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News Dennis Brophy to Receive Accellera Systems Initiative Leadership Award 30 May 2012 Accellera Systems Initiative Hosts User Events at the 2012 Design Automation Conference 23 May 2012 ISCUG 2012 Slated for April 9-10 in Bangalore 29 Mar 2012 Featured Quote "We continue to work with the IEEE to make approved EDA and IP standards available," said Shishpal Rawat, chair of Accellera Systems Initiative. "Through the IEEE Get Program, we provide valuable standards documentation at no cost to the worldwide electronics industry community to support and foster electronic design innovation."... More » Other News From the Industry Synopsys Honors Accellera Systems Initiative with 2012 Tenzing Norgay Interoperability Achievement Award Open SystemC Initiative and Accellera merger paves way for broad interoperability standards MOUNTAIN VIEW, Calif., May 24, 2012 -- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, announced that Accellera Systems Initiative will receive Synopsys’ twelfth annual Tenzing Norgay Interoperability Achievement Award for advancing industry standards that enable interoperable system design flows. More »

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DAC 2012 Freebies, Silicon Valley Special Offer

They seem pretty motivated to get your attendance, if you are in Silicon Valley (or if you can swing a stay on somebody's couch there).

It is something I would recommend if you are job-seeking in this field, even if CA is not where you want to be, it is a great place for networking.

Of course, if you want to be in Colorado in hardware design/verification/EDA, (or even better compiler engineering!) you should definitely drop me an email or a LinkedIn connection  :-)

Cheers, 
Connie L. O'Dell 
Sr. Verification Specialist 
c.odell@co-consulting.net 
303-641-5191 
_____________________________________________ 
CO Consulting - Boulder, CO - http://co-consulting.net

---------- Forwarded message ----------
From: EDA Consortium <events12@edac.org>
Date: Tue, May 29, 2012 at 6:35 PM
Subject: DAC 2012 Silicon Valley Special Offer

...

We're eagerly anticipating the 49th Design Automation Conference in San Francisco next week. Many thousands of design professionals, researchers and 'chipheads' will share the very latest at DAC. May we invite you to join the DAC excitement, in nearby San Francisco? There is free bus service from the south bay, making a day at DAC easier than ever.

Next to our full registration, we can offer complementary registration for the User Track, tutorials, keynotes, and exhibition (details here).  That makes spending a day at DAC more convenient than ever. Please pass this around among your colleagues.

For 2012, we have the most exciting and elaborate program in half a century of DAC legacy. A few of the highlights are:

• Keynotes by Mike Muller (ARM's founder & CTO) and the chief architects of Intel's and IBM's hottest chips on design practices
• Chose from hundreds of presentations on the on latest methods and technologies. 
• 100+ presentations by IC designers from leading companies on design practices in the User Track
• Hard-hitting compact tutorials on System C design, Analog Design, lithography challenges in 10nm and 14nm, etc.
• Dynamic panel sessions on future design trends and hypes, cloud, 3D, tear downs and much much more!
• Over 200 companies lined up in the exhibition, officering a complete coverage of commercial design tools and IP solutions.
• Meet colleagues and old friends during the daily cocktail receptions. 
• Much more! check out the program at http://www.dac.com/dac+2012+conference+program.aspx
• Free bus service from the south bay makes the trip up to San Francisco easy and stress free. 

It would be our pleasure to welcome you at DAC, the place we design meets automation! Please check out http://www.dac.com to see  what DAC has to offer and register today. 

We look forward to see you at 49th DAC, at the home of the 49ers!

Regards,

Bob Gardner
Executive Director
EDA Consortium

EDA Consortium | 111 West Saint John St. | Suite 220 | San Jose | CA | 95113

Denali/Cadence DAC Party Still Alive?: (was: Industry Insights Blog)

I do not know what the attendee screening rules are like, of course, but it is nice to see it continuing...

"... Learn about all Cadence DAC activities, including the Denali Party, here  ..."

Industry Insights Blog

---

Free DAC Breakfasts: HW/SW Co-Development, 28nm/20nm Challenges Posted: 14 May 2012 06:00 AM PDT Don't go into the frenzied activity of the Design Automation Conference (DAC) without a good breakfast! Fortunately, you can get a good breakfast and learn a lot from two events sponsored by Cadence Tuesday, June 5 and Wednesday, June 6 at the 49th DAC in San Francisco.   Tuesday June 5 Addressing Hardware/Software Co-Development, System Integration, and Time to Market Time: 8:00 AM - 10:00 AM (doors open and breakfast is served at 7:30 AM) Location: 270-276 (Moscone Convention Center) This breakfast will feature speakers from Cadence and LSI Corp. Speakers will present the following topics: Cadence System Development Suite overview "Intelligent instrumentation" using the System Development Suite Improving FPGA bring-up time using the Palladium front end (LSI) Real-world system validation using Palladium XP Verification IP catalog update The breakfast session will conclude with a panel discussion in which Cadence technologists and guests will answer your questions about system-level development challenges. Wednesday June 6 The Path to Yielding at 2(x)nm and Beyond Time: 8:00 AM - 9:00 AM (doors open and breakfast is served at 7:30 AM) Location: 270-276 (Moscone Convention Center) This breakfast will include speakers from Cadence, IBM and Samsung. A panel will look at process and design challenges at advanced nodes and discuss what it takes to ramp up to volume production. The panel will examine challenges from the foundry, EDA and customer perspectives. Interested? Learn more about Cadence DAC lunches and breakfasts here Register for lunches and breakfasts here Learn about all Cadence DAC activities, including the Denali Party, here See you in San Francisco! Richard Goering

Free DAC Lunches: Custom/Analog Variability, ARM Low Power Processors in Mixed-Signal Designs Posted: 14 May 2012 06:00 AM PDT There is such a thing as a free lunch - if you're at the 49th Design Automation Conference (DAC) in San Francisco June 3-7. Cadence is sponsoring two lunches at which you can learn about two important technology topics - custom/analog variability, and the use of ARM processors in low-power, mixed-signal designs.   Monday June 4 Overcoming Variability and Productivity Challenges in Your High-Performance, Advanced Node, Custom/Analog Design Time: 12:00 PM - 1:00 PM (doors open and food is served at 11:30 AM) Location: 270-276 (Moscone Convention Center) Speakers at this lunch include Francois Lemery, CAD Project Manager, STMicroelectronics; Vinod Kariat, Fellow, Cadence; and Thomas Volden, Architect, Cadence. Speakers will show why variability is introducing new challenges at advanced process nodes, including layout-dependent effects. Cadence experts will demonstrate a comprehensive flow that can reduce total design time, manage layout-dependent effects, and optimize circuit performance without over-designing. Tuesday June 5 Overcoming the Challenges of Embedding Ultra Low-Power, ARM 32-bit Processors into Analog/Mixed-Signal Designs Time: 12:00 PM - 1:00 PM (doors open and food is served at 11:30 AM) Location: 270-276 (Moscone Convention Center) Speakers at this luncheon include Rob Cosaro, MCU System and Architecture group, NXP; Keith Clarke, VP Embedded Processors, ARM;  John Murphy, Alliance Group Director, Cadence; Mladen Nizic, Engineering Director, Cadence; and Jamie Davey, ARM Alliance Director, Cadence. Speakers will participate in a roundtable discussion showing how you can integrate ARM Cortex-M processors and other design IP into your mixed-signal design more efficiently. Attendees will learn about the advantages of the new Cortex-M0 processor, ARM Cortex-M based MCUs from NXP, and the Cadence low-power and mixed-signal design solution. Interested? Learn more about Cadence DAC lunches and breakfasts here Register for lunches and breakfasts here Learn about all Cadence DAC activities, including the Denali Party, here See you in San Francisco! Richard Goering

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