DVCon 2013: Conference Program is LIVE!

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View the 2013 Conference Program Engage with experts at DVCon 2013! 12 technical sessions, 2 panels, poster sessions, keynote address, 10 tutorials and exhibits! Tutorials: Monday, February 25: Tutorial 1: Lessons from the Trenches: Migrating Legacy Verification Environments to UVM™ Tutorial 2: Increasing Productivity with SystemC in Complex System Design and Verification Tutorial 3: Low Power Design, Verification, and Implementation with IEEE 1801™ UPF™ Tutorial 4: User Experiences at the Forefront of Mixed-Signal Design and Verification Thursday, February 28: Tutorial 5: Fast Track Your UVM Debug Productivity with Simulation and Acceleration                                                            Tutorial 6: We’ve Got You Covered: Practical Advice for Achieving Coverage Closure                                                          Tutorial 7: Higher-Level Verification IP (VIP) Capabilities Accelerate SoC Verification                                                          Tutorial 8: Achieving Visibility into the Functional Verification Process using Assertion Synthesis                                                          Tutorial 9: A Formal Approach to Low Power Verification                                                      Tutorial 10: Pre-Simulation Verification for RTL Sign-Off                                                      Conference Location: DoubleTree Hotel San Jose 2050 Gateway Place San Jose, CA 95110 408-453-4000 www.dtsj.com The discounted room rate for DVCon 2013 is $167 single/double and includes high-speed internet   Be sure to book your hotel by February 1, 2013! Follow DVCon 2013: Media Sponsor: In This Issue Conference Program Tutorials Hotel Reservations Book Exhibit Space Conference by Day MONDAY: FEB. 25 TUESDAY: FEB. 26 WEDNESDAY: FEB . 27 THURSDAY: FEB. 28 Conference Keynote Walden C. Rhines - Mentor Graphics Corp.  BIG Advantages of Exhibiting Book your space TODAY! Exhibiting at DVCon is a proven way to spend quality time with the people you most want to meet - your customers. Contact Stacy Landers 2013 Expo Floor plan Exhibit Contract Sponsorship Opportunities Exhibitor Timeline First Time Exhibitor

1786 18th St. | San Francisco, CA 94107 US

email : Webview : DVCon 2013: Conference Program is LIVE!

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Free SystemC/UVM training for beginners, other Doulos free resources

FREE technical resources and webinars
The KnowHow area of the Doulos website contains an extensive catalog of FREE on-line technical resources.You will find up-to-date articles, papers, presentations and plenty of other useful resources in a variety of media, whatever your field of expertise. Here are some examples:

	Doulos Video Gallery Check out the Doulos Video Gallery for a range of useful video resources covering VHDL, SystemVerilog, Verification Methodologies, SystemC, TLM-2.0 and ARM. View the Doulos Video Gallery now
A Designers Guide to Verilog	The basics of Verilog from a hardware designer's perspective. View the Doulos Designer's Guide to Verilog now
	For a complete beginners guide to using SystemC, download the DoulosSystemC Headstart kit
	Easier UVM - Now or Never? FREE on-demand webinar Why you should (or in a few cases should not) be adopting UVM right now: View this webinar now
	ARM Cortex-A9 FREE on-demand webinar Doulos ARM guru, Dr David Cabanis introduces the core architecture of the ARM Cortex-A9 MPCore processor. View it now
	Embedded Software Resources Download real time embedded software related white papers by industry expert Niall Cooling. View the Embedded Software Resources now

Free SystemC training for beginners

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This Friday - Free on-line training - SystemVerilog/VHDL/SystemC

Webinar: Start date: Duration: Presenter: Summary:

VHDL vs SystemVerilog vs SystemC » October 5, 2012 x1 1 hour session (all time zones covered) John Aynsley, Doulos CTO This webinar will give you an insight into how each of these languages are being used and their relative strengths and weaknesses.

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November 2012

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Webinar: Start date: Duration: Presenter: Summary:

Synthesis-Friendly SystemVerilog » November 2, 2012 x1 1 hour session (all time zones covered) John Aynsley, Doulos CTO This webinar will explore the features of SystemVerilog that are useful for RTL synthesis, showing how the RTL SystemVerilog language constructs have been optimized for productivity and reliability.

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Future on-line training events

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Webinar: Start date: Duration: Presenter: Summary:

Advanced VHDL Verification: OSVVM » TBC x1 1 hour session (all time zones covered) Alan Fitch, Principal Member Technical Staff This webinar will introduce you to Open Source VHDL Verification Methodology (OSVVM): what it does, how to use it, and how it compares with UVM.

Doulos Webinars

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First Steps with UVM - Part 1, Courtesy of Doulos

New! Extended Video with Download: First Steps with UVM - Part 1

Doulos CTO, John Aynsley, presents a simple, complete UVM source code example (which you can download), explaining what is happening and highlighting best practice. You are shown how UVM source code is organized and how to run the example on popular SystemVerilog simulators. More info: UVM - The Universal Verification Methodology

First Steps with UVM: Part 1

From:
http://www.doulos.com/content/email/1206_ScheduleNA.html

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Video tutorial: UVM, Ready, Set, Deploy, thanks to Accellera

Home - Accellera Systems Initiative:

http://www.accellera.org/news/videos/uvmreadysetdeploy

New Video Tutorial – UVM: Ready, Set, Deploy!

It’s been six months since Accellera and the Open SystemC Initiative joined forces to become Accellera Systems Initiative. In that time, we have achieved several milestones in developing standards that address the real needs of system and semiconductor designers.

The Universal Verification Methodology (UVM) standard continues to gain adoption across the verification community. Presented by expert verification methodology architects and engineers at DVCon 2012, the eight-part video tutorial is available at no cost to users and provides an introduction to key UVM concepts and best practices.

See us at the Design Automation Conference, June 4-7 in San Francisco! We will be hosting several events at this year's DAC including a luncheon on the Unified Coverage Interoperability Standard (UCIS), NASCUG meeting, and special birds-of-a-feather sessions. At the luncheon, Accellera Systems Initiative will receive the Tenzing Norgay Award, and will present its 2012 Leadership Award. Events are no charge with advance registration required. Read the latest article on UCIS featured in our newsletter.

Dennis Brophy Receives 2012 Accellera Systems Initiative Leadership Award 

To be presented at our luncheon at DAC in San Francisco on Wednesday, June 6, 2012

Details >>>

DAC 2012

June 6 | San Francisco, CA

• Hosted Luncheon and UCIS Technical Presentation
• Birds-of-a-Feather Meetings
• NASCUG XVIII

Find out more >

SystemC Japan

July 6 | Yokohama, Japan

DVCon 2013

Call for abstracts >

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Recent Happenings  • UVM 1.1b Reference Implementation now available • Accellera Systems Initiative receives 2012 Tenzing Norgay Award from Synopsys. See press release > • May newsletter now available. • John Aynsley receives the 2012Technical Excellence Award.    • IEEE 1666-2011 Now Available for Free Download courtesy of Accellera Systems Initiative. • Open Verification Library (OVL) 2.6release is now available for download. OSCI and Accellera Unite The new organization will leverage the complementary efforts of both groups to create more comprehensive standards. • Welcome from the Chair  • Read what Accellera Systems Initiative members and others are saying • Frequently Asked Questions

News Dennis Brophy to Receive Accellera Systems Initiative Leadership Award 30 May 2012 Accellera Systems Initiative Hosts User Events at the 2012 Design Automation Conference 23 May 2012 ISCUG 2012 Slated for April 9-10 in Bangalore 29 Mar 2012 Featured Quote "We continue to work with the IEEE to make approved EDA and IP standards available," said Shishpal Rawat, chair of Accellera Systems Initiative. "Through the IEEE Get Program, we provide valuable standards documentation at no cost to the worldwide electronics industry community to support and foster electronic design innovation."... More » Other News From the Industry Synopsys Honors Accellera Systems Initiative with 2012 Tenzing Norgay Interoperability Achievement Award Open SystemC Initiative and Accellera merger paves way for broad interoperability standards MOUNTAIN VIEW, Calif., May 24, 2012 -- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, announced that Accellera Systems Initiative will receive Synopsys’ twelfth annual Tenzing Norgay Interoperability Achievement Award for advancing industry standards that enable interoperable system design flows. More »

Featured Videos UVM - Ready, Set, Deploy

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First Steps with UVM Part 1 - YouTube

First Steps with UVM Part 1 - YouTube:

Published on May 14, 2012 by aijnsleij

John Aynsley from Doulos presents a simple, complete UVM source code example (which you can download), explaining what is happening and highlighting best practice. You are shown how UVM source code is organized and how to run the example on popular SystemVerilog simulators.

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DVCon 2012 Verification Paper Archive – UVM, Low Power, Mixed Signal and More! - Industry Insights - Cadence Community

DVCon 2012 Verification Paper Archive – UVM, Low Power, Mixed Signal and More! - Industry Insights - Cadence Community:

DVCon 2012 Verification Paper Archive – UVM, Low Power, Mixed Signal and More!

By Richard Goering on May 1, 2012Comments(0)Filed under: Industry Insights, DVCon, low power, TLM, SoC, Accellera, verification, IP, Mixed-Signal, mixed signal, Functional Verification, UVM, SystemVerilog, assertions, SVA, coverage, UVM-MS, debugging, PSL, virtual prototypes, DVCon 2012,covergroups, DVCon presentations, DVCon papersIn late April, a wealth of information on IC functional verification became available at the DVCon web site. Both papers and slides are now available for dozens of high-quality presentations given at the DVCon 2012 conference, which was held Feb. 27-March 1, 2012 in Santa Clara, California. You can view the list of sessions here.
Cadence contributed heavily to DVCon this year, and what follows is a listing of Cadence-authored or co-authored papers now available for viewing and downloading. Happy reading!
Session 1:  Low Power Techniques
Paper:  The Case for Low-Power Simulation-to-Implementation Equivalence Checking
Presented by: Himanshu Bhatt, Cadence
Summary: I attended this paper, and found it to be a good summary that shows how equivalence checking fits into the low-power verification flow. While power formats unify intent, the paper notes, implementation and verification tools may interpret the information differently.  Equivalence checking can formally prove that simulation matches the original power intent and RTL.
Session 1P: Poster Session 1
Paper: PSL/SVA Assertions in SPICE
Presented by: Donald O'Riordan, Cadence
Summary: This paper shows how Property Specification Language (PSL) and SystemVerilog Assertions (SVA) assertion semantics can be extended to, and evaluated within, a SPICE-based simulator. It presents multiple examples and simulation results.
Paper: New Challenges in Verification of Mixed-Signal IP and SoC Design
Presented by: Qi Wang, Cadence
Summary: Mixed-signal blocks with advanced power management techniques can pass simulation but fail in silicon. This paper proposes that a static verification methodology can help catch electrical failures.
Session 2: UVM Techniques
Paper: Register This! Experiences Applying UVM Registers
Presented by: Kathleen Meade, Cadence
Summary: Controlling and monitoring registers and memories comprises a large part of typical functional verification projects. This paper shows how the Accellera UVM-REG register and memory package can help, and provides some practical guidelines for register management gleaned from real project experience.
Session 2P: Poster Session 2
Paper: UVM Do's and Don'ts for Effective Verification
Presented by: Kathleen Meade, Cadence
Summary: This presentation provides tips and best practices using specific pointers and code examples, gathered from live projects worldwide. Topics include configuration, the objection mechanism, the register package, and transaction level modeling (TLM).
Session 4: Verification Benchmarking and Efficiency
Paper: Yikes! Why is My SystemVerilog Testbench so Slow?
Presented by: Justin Sprague, Cadence
Summary: While SystemVerilog added many useful new features, many verification engineers have experienced slower simulation. This paper shows why - and tells what you can do about it.
Session 6: Mixed-Signal Verification
Paper: From Spec to Verification Closure: A Case Study of Applying UVM-MS for First Pass Success to a Complex Mixed-Signal SoC Design
Presented by: Neyaz Khan, Maxim
Summary: This paper shows why metric-driven verification and UVM are needed for mixed-signal verification, and presents an example based on a noise cancelling receiver block within a mixed-signal SoC. I attended and wrote a blog post about this paper.
Session 7: Verification and Debugging Tips
Paper: Memory Debugging of Virtual Prototypes with TLM 2.0
Presented by: George Frazier, Cadence
Summary: Memories are commonly modeled as TLM 2.0 components in SystemC-based virtual prototypes. This paper shows how TLM 2.0 memory debugging can be used to investigate problems familiar to virtual prototype designers.
Session 8: Getting to Coverage Closure
Paper: Bringing Continuous Domain into SystemVerilog Covergroups
Presented by: Prabal Bhattacharya, Cadence
Summary: This paper proposes a set of requirements for specifying functional coverage in an analog or mixed-signal block. It explains how the real number data type can be introduced into a SystemVerilog coverpoint specification, enabling a complete coverage specification for a mixed-signal verification environment.
Note: An audio archive of the DVCon 2012 panel, "The Resurgence of Chip Design," is available here. You can listen to individual sections of the panel or download the full MP3 file. My blog summary of the panel is locatedhere.
Richard Goering

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Magma Assimilation, Forte (news + jobs), DVcon, Specman e, Atrenta, Calypto

If you care at all about EDA and verification, you should definitely get on John Cooley's mailing list.  Good stuff!

Cheers,
Connie "I Was Assimilated by Cadence, But I Got Better" O'Dell
Sr. Verification Specialist
c.odell@co-consulting.net
303-641-5191
_____________________________________________
CO Consulting - Boulder, CO - http://co-consulting.net

---------- Forwarded message ----------
From: John Cooley
Date: Thu, Mar 8, 2012 at 3:32 AM
Subject: TSMC 28 nm, DVcon, Specman e, Atrenta, Calypto, Forte, SKILL

 "I feel bad for the Magma employees being absorbed by the
  Synopsys Borg.  Today they learn that resistance is futile."

      - An EDA Vendor on SNPS-LAVA merger completing

-------------------------------------------------

 HW forums cite rumor that TSMC suddenly halted 28 nm production
    http://www.deepchip.com/items/0500-01.html

 Brett's quickie trip reports on both DVcon'12 and NASCUG'12 confs
    http://www.deepchip.com/items/0500-02.html

 CDNS too afraid of SV sales to support SNPS/MENT Specman "e"
    http://www.deepchip.com/items/0500-03.html

 Three chip designers hands-on evals of Atrenta Spyglass Power
    http://www.deepchip.com/items/0500-04.html

 We cut another 9% of power using the Calypto RTL PowerPro tool
    http://www.deepchip.com/items/0500-05.html

 Shiv compares IC Manage, CVS, and Subversion for digital design
    http://www.deepchip.com/items/0500-06.html

 I designed a USB 3.0 core using SystemC and Forte Cynthesizer
    http://www.deepchip.com/items/0500-07.html

 Huh? SKILL sklint() already built into the Virtuoso environment
    http://www.deepchip.com/items/0500-08.html

-------------------------------------------------

 Docea Power to unveil AceThermalModeler at upcoming DATE'12
    http://www.deepchip.com/look/see120308-01.html

 Jasper CEO Kathryn Kranen in San Jose Mercury News interview
    http://www.deepchip.com/look/see120308-02.html

 San Jose, CA - Forte seeks SystemC Cynthesizer field engineers
     http://www.deepchip.com/jobs/033.html

SystemC/UVM/Verification Learning opportunities at DVCon 2012, San Jose, CA

From: Doulos Training <doulos@email.doulos.com>
Date: Wed, Feb 22, 2012 at 5:02 PM
Subject: Learning opportunities at DVCon 2012

ALL THE LATEST NEWS FROM DOULOS View this email in a web page / Change how you receive emails from Doulos Event news: DVCon 2012 - San Jose, CA Doulos at DVCon (Booth 701): World first tutorial on new standard SystemC User Group meeting SystemVerilog/UVM at DVCon Tutorial on the new SystemC standard Doulos CTO, John Aynsley is organizing the world's first tutorial explaining the features of the new SystemC standard, on Monday February 27, at DVCon 2012 in San Jose next week. This tutorial represents a unique chance to improve your understanding of SystemC as well as giving you a kick start with the new language standard, including the marriage of the SystemC and TLM-2.0 libraries. Full SystemC tutorial session details SystemC training and support The Doulos Guide to SystemC Register for DVCon 2012 Great agenda at NASCUG XVII There are plenty of useful, user-focussed papers and presentations making up the North American SystemC User Group meeting located at DVCon. Doulos specialist, David C Black, will be taking a look at some of the features of C++2011 and illustrate how they could change the way code is written. More details about this meeting on Monday February 27 Other recommended learning opportunities at DVCon 2012 Monday February 27: UVM: Ready, Set, Deploy Tuesday February 28: Easier SystemVerilog with UVM: Taming the Beast Wednesday February 29: Comprehensive Register Description Languages Catch up with the Doulos team at Booth 701 - DVCon floorplan

For more information please call the Doulos team on 1 888 GO DOULOS or email info.usa@doulos.com
Copyright 2012 Doulos Limited. All rights reserved.
Please add doulos@email.doulos.com to your address book


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