North American SystemC User's Group Meeting (NASCUG)
Monday, June 32:00-6:00 pm
Ballroom D
Pre-registration is required for this free event. Seating is limited, so register today!
A central component of the half-day user's group meeting is a number of short user experience presentations discussing techniques of design, modeling and verification using SystemC.
Agenda available soon on nascug.org.
Join us at DAC events dedicated to technical standards!
Accellera Breakfast and Town Hall Meeting
Topic: "The Standard for Low Power Design and Verification is here! What's next?"
Monday, June 3
7:00-8:45 am
Ballroom D
7:00-8:45 am
Ballroom D
Register Here >>>
Pre-registration is required for this free event. Seating is limited, so register today!
Pre-registration is required for this free event. Seating is limited, so register today!
Moderated by: Ed Sperling, System-level Design
Panelists:
- John Biggs, Consultant Engineer, ARM
- Sushma Honnavara-Prasad, Sr. Staff Engineer, Broadcom
- Qi Wang, Solutions Group Director, Cadence
- Erich Marschner, Verification Architect, Mentor Graphics
- Jeffrey Lee, Staff Corporate Application Engineer, Synopsys
North American SystemC User's Group Meeting (NASCUG)
Monday, June 32:00-6:00 pm
Ballroom D
Register Here >>>
Pre-registration is required for this free event. Seating is limited, so register today!
A central component of the half-day user's group meeting is a number of short user experience presentations discussing techniques of design, modeling and verification using SystemC.
Agenda available soon on nascug.org.
IP XACT Tutorial: "A Practical Guide to Packaging IP and Assembling SoCs Using the IP-XACT- IEEE1685 Standard"
Monday, June 311:00-1:00pm; 2pm-4pm and 5pm-7pm
Location: 14
A practical guide to packaging IP and assembling SoCs using the IP-XACT- IEEE1685 Standard. This all-day DAC tutorial will appeal to those new to the IP-XACT- IEEE1685 standard as well providing additional insight into more advanced IP-XACT topics. The tutorial will be presented by IP-XACT experts and will begin with a brief introduction to IP-XACT, followed by a deeper dive of the core IP packaging and design/assembly metadata concepts of IP-XACT and concludes with an examination of the typical flows that can utilize this metadata. Read more on the DAC website >
Attendees will initially be through typical IP Packaging metadata e.g. components, bus definitions, bus interfaces and HW/SW interface representation. The focus will then move to integration-oriented topics and explore how hierarchical designs are represented and connected. Some advanced integration topics are introduced that explore how system-memory mapping are represented as well as how configurability is addressed. The final section then explores how this component and design metadata can be processed and presents several different example flows.
The presentation technique will focus more on visually presenting the IP-XACT concepts rather than walking through XML snippets.
Organizers:
- David Murray / Duolog Technologies Ltd., Galway, Ireland
- Kathy Werner / Southwest Reuse, Austin, TX
- David Murray / Duolog Technologies Ltd., Galway, Ireland
- John Eaton / Ouabache Designworks, Vancouver, WA
- Vasant Kumar Easwaran / Texas Instruments India Pvt. Ltd., Bengaluru, India
- Mark Noll / Synopsys, Inc., Portland, OR
- Kamlesh Kumar Pathak / STMicroelectronics, Greater Noida, India
- Sylvain Duvilliard / Magillem Design Services, Cannes, France
DAC Birds-of-a-Feather Meeting:
Topic: "Creating a Standard for Interoperability of Multi-language Verification Environments and Components"Tuesday, June 4
7:00-9:00pm
Room 11AB
Sign up here >>>
Roughly 18 months ago, the Accellera Board tasked representatives from six electronics companies to define a standard for multi-language verification. Warren Stapleton, chair of the Multi-Language Working Group (MLWG), will review the progress of the group in an open forum. Please join us to learn more about this exciting topic.
The audience for this session is IP stakeholders — the authors, users, and EDA tool vendors. The intent is to provide enough detail for a high-level overview suitable for members of the IEEE 1800 and P1076 working groups and balance that with enough introductory material to explain the concepts to anyone interested.
Accellera Systems Initiative is calling for member participation in the newly formed Multi-Language Working Group.
DAC Birds-of-a-Feather Meeting:
Topic: "Exploring the IEEE P1735-IP Protection Standard"Tuesday, June 4
7:00-9:00pm
Room 12AB
Sign up here >>>
P1735 has developed recommendations for IP Protection that soon will become a standard. This contains both recommendations and extensions to the IEEE protection pragmas in the SystemVerilog and VHDL LRMs. Its overall goal is to enable IP authors to evaluate and use IP protection to more effectively deliver their IP for use in an interoperable tool flow for a wider IP user community. This session will explain the use models for this protection and how it can work effectively in an interoperable tool flow. It will explain the extensions to support or improve key management, licensing, rights management, and visibility.
Accellera Systems Initiative, 1370 Trancas Street, #163, Napa, CA 94558
Copyright Accellera Systems Initiative. All Rights Reserved. www.accellera.org
Copyright Accellera Systems Initiative. All Rights Reserved. www.accellera.org
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