Cheers,
Connie
From: Electronic Design Update: Power and Analog <edupdate@email.electronicdesign.com>
Date: Thu, Jul 22, 2010 at 1:31 PM
Subject: Hybrid and Electric Vehicles Present Opportunities for Design Engineers
To: c.odell@ieee.org
|
Thursday, July 22, 2010
Hybrid and Electric Vehicles Present Opportunities for Design Engineers
Cheers,
Connie
From: Electronic Design Update: Power and Analog <edupdate@email.electronicdesign.com>
Date: Thu, Jul 22, 2010 at 1:31 PM
Subject: Hybrid and Electric Vehicles Present Opportunities for Design Engineers
To: c.odell@ieee.org
Wednesday, July 14, 2010
System Verilog Open Enrollment--Longmont, CO, 8/9/10
Date: Wed, Jul 14, 2010 at 1:47 PM
Subject: Sutherland HDL Open Enrollment--Longmont, CO
Sutherland HDL is offering an open-enrollment SystemVerilog training workshop in Longmont, Colorado, August 9-13. Registration closes at 9:00 AM PDT July 26th, so that the training materials can be printed and shipped.
There are three options for training, allowing you to focus on your individual training needs. The two courses offered this week are customized to offer the information you need in a minimal amount of time. The concepts of advanced SystemVerilog that are common to both courses will be taught on Wednesday. For a detailed outline of either course, please contact Sutherland HDL at stuart@sutherland-hdl.com. When 2 or more engineers from the same company attend, they each receive an additional 5% discount.
Option 1: (Mon-Wed)
Comprehensive Verilog and SystemVerilog for Design and Synthesis (3-days)
Longmont, Colorado, August 9-11 $1,800 per student (~10% off our standard 3-day price)
This is the perfect workshop for engineers to become instant experts in modeling digital designs that simulate and synthesize correctly using SystemVerilog. Self-taught users of SystemVerilog will also find this workshop extremely valuable. We often receive comments about how much even those who are current Verilog users learn from this comprehensive workshop.
This course covers the same lecture information as the full 4-day course, without the final lab work.
Option 2: (Wed-Fri)
SystemVerilog Testbench for Verilog Verification Engineers (3-days)
Longmont, Colorado, August 11-13 $1,800 per student (~10% off our standard 3-day price)
This workshop is ideal for verification engineers that are already familiar with Verilog, and need to become experts with SystemVerilog's advanced, object-oriented verification constructs. Topics include inheritance and polymorphism as it applies to verification, constrained random testing, functional coverage, and an overview of assertions. This workshop is intended for verifications engineers that have Verilog experience.
Option 3: (Mon-Fri)
Longmont, Colorado, August 9-13 $2,900 per student (~10% off our standard 5-day price)
Attend all 5 days and receive training in both design and verification.
Registration information can be found at http://www.sutherland-hdl.com
Onsite Workshops
Sutherland HDL can also provide on-site training at your company when and where you need training! There is a 5 student minimum charge for on-site training. All that is needed is a simple meeting room; Sutherland HDL provides the software for labs and a portable server with an isolated network.
We hope to see you soon at this upcoming workshop! Please forward this e-mail to any of your co-workers that might benefit from expert SystemVerilog training.
Stuart Sutherland
President and expert trainer
Sutherland HDL, Inc.
Portland Oregon
+1.503.692.0898
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
At Sutherland HDL we hate unsolicited e-mail just as much as you do. We only send out announcements regarding our training schedule a few times each year. You are on are e-mail list because you have contacted us in the past regarding our services, or have attended an engineering conference where you indicated that you would like further information. If you do not wish to receive these announcements, just reply to this message asking to be removed from our mailing list, and we will do so immediately. Really.
Tuesday, July 13, 2010
How to (tactfuly) answer illegal interview questions
Design&Verification: Mentor @ DAC Extended Schedule- July 13, 2010
http://ow.ly/2aIz9
Looks interesting (and free) to me. From the LinkedIn
FPGA/CPLD Design Group
Connie