There are, obviously a lot of useful SystemC resources. Just FYI, I found the videos below useful for a little update on the latest thoughts on SystemC. There are good insights related both to verification of SystemC, as well as high-level synthesis (HLS) of SystemC. When you watch the videos you can also download handouts for most of them (sadly not for John Aynsley's long but very good presentation). The first set of videos is almost like spending a half-day at DVCon 2010 earlier this year, which sadly I missed this year! They also have some videos on YouTube but some of them are very short, so the netbook wins over the iPad as an educational platform once again. :-)
If you have more time, the following books have yet more detail. The David C. Black book is so far the most-recommended SystemC book I have found. The new TLM-Driven design book is currently price-reduced on Amazon to ~$85. The latter also is reported to be somewhat vendor-specific, but it is not clear what else really covers the HLS synthesis process from top to bottom.
And of course, as always, Doulos has all sorts of great stuff:
http://www.doulos.com/knowhow/systemc/
like this below, and much more:
- NEW:Functional Coverage without SystemVerilog How to collect functional coverage information using VHDL or SystemC
- Dealing with Deprecated Features in SystemC 2.2
- New SystemC Standard
- Tutorial
- FAQ
- Resources
- Using Doxygen
- Utilities
Also, I welcome any perspective readers are willing to share on the following questions at the top of my brain:
Is there an open-source code coverage solution that works pretty well for SystemC, and is not too painful to set up? Or if you recommend a vendor solution, is it expensive, and is it worth it?
Is there an open-source linting solution that works pretty well for SystemC, and is not too painful to set up? Or if you recommend a vendor solution, is it expensive, and is it worth it?
And seemingly unrelated, but interesting to me nonetheless, as I assume that formal (property) verification is too immature for SystemC:
Do you know of a vendor-supplied formal (property) verification tool that is moderately priced, has a good verilog parsing engine, and is good enough at pruning away the parts of the logic irrelevant to a given property that it would be practical to apply to apply with relatively little design knowledge at a relatively high level, without one having to hand-abstract the design in a painful way? My immediate interest would not be formal property proof, but rather a coarse kind of design exploration of some fairly basic but pervasive functionality. And it is always nice if it has a vaguely english-like property language, of course.
(Don't tell me what is wrong with this question, I already know that this is not a recommended methodology, and that I am asking for a lot. I used to recommend FV methodology. Sheesh.)
Connie
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