DVCon: UVM Tutorial (Universal Verification Methodology)

Can't go, have too much work already, but maybe you can!

Cheers, 
Connie L. O'Dell 
Sr. Verification Specialist 
c.odell@co-consulting.net 
303-641-5191 
_____________________________________________ 
CO Consulting - Boulder, CO - http://co-consulting.net

---------- Forwarded message ----------
From: DVCon 2011 <news@mpassociates.com>
Date: Tue, Jan 25, 2011 at 12:49 PM
Subject: Invitation to Learn about Accellera's Universal Verification Methodology (UVM) from Experts at DVCon
 

Accellera's Verification Intellectual Property (VIP) committee members invite you to learn about our new Universal Verification Methodology (UVM™) directly from the experts during a daylong tutorial at DVCon. For a detailed agenda of the technical content, please click here. To register for this event and our Accellera luncheon and Town Hall session please click here.

 

Verification has evolved into a complex project that often spans internal and external teams, but the discontinuity associated with multiple, incompatible methodologies among those teams has limited their productivity.  The UVM standard addresses verification complexity and interoperability within companies and throughout the electronics industry for both novice and advanced teams while also providing consistency. It defines a standard for the creation, integration, and extension of the UVM Verification Component (UVC) and the verification environments that scale from block to system. Accellera's VIP committee has been working hard to create the UVM for the past 18 months. Expert users, methodology engineers and tool developers have put together not just the standard specification but also a source code reference implementation for immediate deployment in complex SoC verification projects. Our tutorial will be presented by those experts.

 

Between the introductory and Transaction Level Modeling (TLM) sessions in the morning and the phasing and registers sessions in the afternoon, please join us for our lunch time Town Hall discussion on the UVM, SystemC and Transaction Level Modeling (TLM). A combined UVM and SystemC panel of experts will field questions and provide insights into how to bridge the abstraction gap between system-level verification and implementation level environments.  

You can find out more about UVM by visiting http://www.accellera.org/activities/vip.  

 

See you at DVCon.

Shishpal Rawat, Accellera Chair