"Verification is Due for an Image Overhaul" Harry Foster/MGC

Harry knows his real-world formal verification, both as a customer (HP) and as a vendor, so his articles are highly recommended!

Cheers,
Connie

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From: Verification Tech News <info@mentoremail.com>
Date: Thu, Sep 16, 2010 at 10:00 AM
Subject: Verification is Due for an Image Overhaul - Learn More Inside
To: c.odell@co-consulting.net

Hello, We are pleased to share with you the latest Verification news and information and hope you enjoy this month's issue. News   »   Verification is overdue for an image overhaul - Formal verification is the key to 40 more years of chip design, by Harry Foster Formal verification, or specifically formal property checking, is one of those ideas in technology that, for many people, has never fully lived up to its promise. It's easy to get a sense of the origin and growth of the specific term in the technical literature by simply doing a search through the IEEE Xplore database. What you will find is that the references to the term "formal verification," which is the proof of properties on designs using logic rather than testing, dates back to the early 1980s. Formal verification is long overdue for nothing less than an image overhaul. Unfortunately, this project is unlikely to attract the attention of high priced marketing wizards, who understandably find consumer brands and political campaigns more compelling than EDA. That leaves those of us who are technologists to tackle this one. Any volunteers? No? Then here goes (with tongue occasionally planted in cheek).      Blogs     »   Redefining Verification Performance (Part 2) by Harry Foster In part 1, I gave a few examples of different ways of thinking about getting more work done by finding solutions that increase amount of work accomplished per cycle, instead of just a brute-force approach to the problem. Before I talk about advanced verification solutions, I want to talk about why performance even matters.     »   Making formal property checking easy to use by Ping Yeung For years one of the objectives in EDA has been to make formal property checking easy to use and its results easy to understand. With the Automatic formal check feature, I think we have made significant progress in this area. The feature, which predefines a set of assertion rules to look for design issues automatically, makes formal technology accessible to users who are not yet ready to write properties in System Verilog Assertion (SVA) or Property Specification Language (PSL). To make it easier to comprehend problems in the design, the tool highlights the violations back to the RTL code. Automatic formal check focuses on three areas inadequately addressed by dynamical simulation.     »   Companion OVM Cookbook Examples Kit also offered for download by Dennis Brophy Several months ago, the OVM Cookbook and the Examples Kit were made available for online use at the Verification Academy. This proved to be a great help to accelerate the skill level of new OVM users. Given the number of new projects that have deployed OVM and the number of new engineers that now need to use OVM, there is increased demand for practical and useful information found in the Cookbook. One can see the OVM World community continues to grow. The same needs from that community to invest in bettering their OVM knowledge and skills is just as needed as those who are members of the Verification Academy. For that reason, we are making the OVM Cookbook and the Examples Kit available for free download from OVMWorld.org.     »   View these post plus many others at the VerificationHorizonsBlog Technical Resources On Demand Web Seminar Presentations   »   Effective Debug of Embedded Processor-based Designs What You Will Learn: To identify and understand the challenges of using embedded code running on the embedded processor for HW verification How Codelink accelerates the diagnostic and debug phase of your processor-based SoC design Advantages of using embedded code for HW verification Download this presentation   »   Eliminating Clock-Domain-Crossing Bugs As many ASIC/FPGA designers of multi-clock designs already know, experiencing clock-domain crossing (CDC) problems is painful. Simulation alone typically doesn't catch CDC bugs, resulting in failing silicon that is extremely difficult and time-consuming to debug and oftentimes requires re-spinning the design. This presentation teaches viewers about the types of problems associated with clock domain crossings, the things you can do to avoid these issues, and how to apply an automated verification solution to ensure your design is free of CDC issues. Download this presentation   »   Finding the Toughest Bugs with Formal Verification As designs get more complex, verification cycles increase dramatically while quality hangs in the balance. As a result, many companies are looking for a better methodology to help them achieve improved verification productivity, predictability and quality. This seminar explains how formal verification can most effectively be used alongside simulation to allow design and verification engineers to find more bugs, earlier in the design process. Download this presentation Technical Events      Accelerating Coverage Closure with Intelligent Testbench Automation Web Seminar     »   Wednesday, September 29th 9:00am - 10:00am US/Pacific Accelerate functional coverage closure in today's complex designs using Mentor Graphics proven methodology, freeing up resources to achieve more verification, resulting in 10x to 100x faster funcitonal coverage closure. Find out more about this complimentary web seminar      Clock-Domain Crossing Verification for FPGAs Web Seminar 9:00am US/Pacific, September 23rd, 2010     »   Today FPGA designers are equally plagued by clock-domain crossing (CDC) problems as ASIC designers are. Simulation alone doesn't catch the CDC bugs, resulting in an extremely difficult and time-consuming to debug process in the lab. This seminar teaches attendees about the types of problems associated with clock domain crossings, the things you can do to avoid these issues, and how to apply an automated verification solution to ensure your FPGA is free of CDC issues. 0-In CDC supports the leading FPGA vendors. Includes a demonstration. More information and Register Have a friend or colleague that would like this newsletter? Feel free to pass it on!   Tom Fitzpatrick Verification Technologist Mentor Graphics Corporation http://www.mentor.com/products/fv If you do not wish to receive future Verification Technical News updates, please update your subscription . Mentor Graphics 8005 SW Boeckman Road, Wilsonville, OR  97070  United States  800-547-3000 or 503-685-8000

In this Issue   News   Blogs Technical Resources Technical Events   Accelerating Coverage Closure with Intelligent Testbench Automation Web Seminar   Clock-Domain Crossing Verification for FPGAs Online seminar