Don't let John fool you, it's a very useful list...
Cheers,
Connie
DeepChip.com (Lots of other good stuff also) ...
6.)
Mentor Catapult C synthesizes C/C++/SystemC to production quality RTL. Now does incremental synthesis for ECOs plus it lets SystemC users synthesize TLM models to create TLM-based virtual prototypes. Used by Qualcomm, Hitachi, Ericsson, ST, TI, Telegent, Panasonic, Fuji Xerox, Toshiba, Fujitsu, Sanyo. (booth 1542) Ask for Thomas Bollaert.
Forte Cynthesizer does SystemC synthesis to Verilog RTL of control and datapath designs. Brett's showing a "bus-based system with complex interfaces in pin and TLM w/ highly abstract coding styles, pipelined memories, untimed and timed code, and full SystemC support. Sony, Realtek, Samsung, Toshiba, Ricoh, Fujitsu, Sanyo, Megachips use it. (booth 3417) Ask for Brett Cline. Freebie: caricatures
Cadence C-to-Silicon Compiler synthesizes SystemC TLM to Verilog RTL. They're very proud it's in the whole proprietary CDNS flow. Will demo an ECO. Used by Fujitsu, Renesas, TI, Freescale, Casio, Hitachi. (booth 2237) Ask for Mark Warren. Freebie: t-shirt
Calypto SLEC 6.0 is *the* C/C++/SystemC equivalency checker. Now has a new word-level solver for inductive setups, SystemC 2.2 support, automatic wrapper and setup generation, CDNS C2S clock-gating, resets. (booth 2012) Ask for Anmol Mathur. Freebie: none
Carbon SoC Designer Plus creates cycle-accurate SystemC models of your chip. "Swap from the 100s of MIPS performance to 100% accuracy at any software breakpoint." Samsung, ST, ST-Ericsson, LG, Huawei, Broadcom use it. (booth 1914) Ask for Bill Neifert. Freebie: none
CoFluent Studio does ESL modeling. New release v4.0 can do automatic generation of SystemC code from graphics for TLM-2.0 LT/AT and SCML2 interoperability. Has an Eclipse-based C++ debugger where changes in user-reserved areas in generated code is propagated back into your graphical model. Nokia, RIM, ST, Canon, Seagate, Toyota uses it. (booth 1815) Ask for Laurent Isenegger. Freebie: none
Bluespec BDW is a GUI for the development, analysis and debug of high-level models, transactors, stimulus generators using Bluespec System Verilog (BSV). Now does source debug with designs in Verilog simulation/emulation or FPGA prototype. "This is enabled by BSV's 100% architectural transparency, which is different from high-level designs that are C-based." Used by Fujitsu, IBM, Intel and Qualcomm. (booth 3031) Ask for George Harper. Freebie: a book on Bluespec
Mentor Vista does TLM modeling style architecture design and virtual prototyping, links to MENT embedded and ESL-to-RTL SoC verification. Used by Honeywell. (booth 1542) Ask for Jon McDonald.
Target Compiler MP Designer automatically parallelizes C code across customer-defined multi-core architectures. (i.e. load balancing) NXP used it to get 2.9x on a new 3-DSP architecture, compared to a single DSP, with an instruction-cycle utilization of 97% on each. (booth 2227) Ask for Erik Duymelinck. Freebie: post-it pads
Cadence SDS/VSP does HW/SW co-design "from architectural-level SW development through system validation to post-RTL prototyping." Does SystemC and UVM. Used by firmware/software teams at ARM, Nvidia, Western Digital. (booth 2237) Ask for Leo Drucker.
ApS Brno Codasip uses an architectural description language called "Codal" and building blocks called "ASIPs" that all synthesizes to Verilog HDL with known area, power, timing. They're new to DAC. (booth 3218) Ask for Karel Masarik. Freebie: none
Mentor Embedded Sourcery CodeBench provides a "complete C/C++ dvlpmnt environment for embedded software design." It won the Embeddy Award at the recent ESC 2011. (booth 1542) Ask for Stephen Olsen.
...
Lots of other good stuff...
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