REMINDER Friday 10AM FtC AMD: IEEE SSCS Seminar - A 32nm 3.1 Billion Transistor 12-Wide-Issue Itanium(R) Processor for Mission-Critical Servers by Reid Riedlinger (Intel, Fort Collins, CO)

If this interests you, non-members are welcome; it's a good idea to RSVP so they know you are coming, and to be on time...

Cheers, 
Connie L. O'Dell 
Sr. Verification Specialist 
c.odell@co-consulting.net 
303-641-5191 
_____________________________________________ 
CO Consulting - Boulder, CO - http://co-consulting.net

---------- Forwarded message ----------
From: Loke, Alvin <Alvin.Loke@amd.com>
Date: Thu, Oct 13, 2011 at 1:43 PM
Subject: REMINDER: IEEE SSCS Seminar - A 32nm 3.1 Billion Transistor 12-Wide-Issue Itanium® Processor for Mission-Critical Servers by Reid Riedlinger (Intel, Fort Collins, CO)

When: Friday, October 14, 2011 10:00 AM-11:15 AM (UTC-07:00) Mountain Time (US & Canada).

Where: AMD Fort Collins campus (NE corner of Harmony and Ziegler)

 

Note: The GMT offset above does not reflect daylight saving time adjustments.

 

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DETAILS http://ewh.ieee.org/r5/denver/sscs/2011_10_Riedlinger.html

 

RSVP            http://gomartin.net/sscs/2011/rsvp_2011_10_14.htm

 

TITLE           A 32nm 3.1 Billion Transistor 12-Wide-Issue Itanium® Processor for Mission-Critical Servers by Reid Riedlinger

 

ABSTRACT

This presentation is an extended encore of a contributed paper delivered at the 2011 International Solid-State Circuits Conference in San Francisco, CA.

The next generation in the Intel® Itanium® processor family, code named Poulson, has eight multi-threaded 64 bit cores. Poulson is socket compatible with the current Intel® Itanium® Processor 9300 series (Tukwila). The new design integrates a ring-based system interface derived from portions of previous Xeon® and Itanium® processors, and includes 32MB of Last Level Cache (LLC). The processor is designed in Intel®'s 32nm CMOS technology utilizing high-K dielectric metal gate transistors combined with nine layers of copper interconnect. The 18.2×29.9mm2 die contains 3.1 billion transistors, with 720 million allocated to the eight cores. A total of 54MB of on die cache is distributed throughout the core and system interface. Poulson implements twice as many cores as Tukwila while lowering the thermal design power (TDP) by 15W to 170W and increases the top frequency of the I/O and memory interfaces by 50% to 6.4GT/s.

 

BIOGRAPHY OF SPEAKER

Reid Riedlinger received his MSEE from Montana State University in 1993. He then joined Hewlett-Packard and worked on various PA-RISC and IPF processors. In 2004, Reid joined Intel Corporation as a Principal Engineer leading the post silicon debug of Montecito, a dual core IPF processor. On Poulson, he was the project lead for the development of the core as well as circuit methodology and is currently responsible for leading the definition of Intel's future generation of Itanium processors. He holds 18 US patents and has been an author on several internal and external conference papers.