17th NASCUG Meeting
27 February 2012
| 8:30 - 9:00 AM | Registration |
|---|---|
| 9:00 - 9:10 AM | Welcome, Agenda & NASCUG IntroductionTor Jeremiassen, Texas Instruments, USA |
| 9:10 - 9:25 AM | Accellera Systems Initiative UpdateShishpal Rawat, Chairman, Accellera Systems Initiative View presentation |
| 9:25 - 9:55 AM | Roundtable: Leveraging Synergy: Future Opportunities with SystemCModerated by Ed Sperling, System Level Design |
| 9:55 - 10:20 AM | What does C++2011 mean to SystemC?David C Black, Doulos, USA View presentation View details |
| 10:20 - 10:45 AM | Synchronization between a SystemC-based Off-line Restbus Simulator and a Hardware-In-the-Loop FlexRay NetworkGilles Bertrand Defo, University Of Paderborn, Germany View presentation View details |
| 10:45 - 10:55 AM | Break |
| 10:55 - 11:20 AM | Extending Fixed Sub-systems at the TLM Level - Experiences from the FPGA WorldFrank Schirrmeister, Cadence, USA View presentation View details |
| 11:20 - 11:45 AM | A Generic Language for Hardware & Software, Are We There Yet? An Explorative Case Study Examining the Usage of SystemC for Multicore ProgrammingSushil Menon, University of Pennsylvania, USA View presentation View details |
| 11:45 AM - NOON | Closing Remarks and Prize Drawing Jack Donovan, Duolog, UK |
Abstracts
What does C++2011 mean to SystemC?
In September of 2011, ISO approved an update to the C++ standard, which is known variously as ISO/IEC 14882:2011, C++0x and C++11. This presentation will take a quick look at some of the features and illustrate how they could change the way we write code. Discussion will also include potential impacts to performance and code quality. Code examples will be given with comments on experiences using the new features and what limitations were encountered.
Synchronization between a SystemC-based Off-line Restbus Simulator and a Hardware-In-the-Loop FlexRay Networ
Residual bus simulation (restbussimulation) is a method used in particular for the design of automotive software typically consisting of distributed controller nodes communicating via a bus. A typical use case is the integration of newly developed functionality (features) into an existing system. To achieve this, the residual bus simulator has to provide messages from non-existing ECUs to the rest of the system at runtime. This enables the test and/or validation of new functionality in an early stage of the development process by means of simulation.
In this paper we present an approach for synchronization between an off-line residual bus simulator implemented in SystemC and a Hardware-In-the-Loop (HIL) system. The residual bus simulator encapsulates functional SystemC models of non-existing nodes. Due to the lack of the real-time simulation support of SystemC, not all the data generated by physical nodes might be received and processed "on time" by the residual bus simulator as the execution speed and order of the SystemC processes can vary. Furthermore our approach makes use of a special downsampling method. During the downsampling process special data such as peaks are detected and can either be ignored or processed. The evaluation of our approach was conducted using a steer-by-wire demonstrator.
Extending Fixed Sub-systems at the TLM Level - Experiences from the FPGA World
One of the most interesting steps of progress towards effective SystemC based system-level design and emphasis on the importance of embedded software has recently come from the world of FPGAs, making available devices combining programmable logic of up to several million ASIC gate equivalents with hard implementations of ARM Cortex-A9 based multiprocessor sub-systems.
The Xilinx Zynq platform encourages extensibility with user logic at the TLM level by offering an "Extensible Virtual Platform", which means design teams can create using custom SystemC models a virtual prototype for software development even before the RTL of the user defined logic is developed, either by hand or using high-level synthesis.
This presentation will report on the user experiences of extending at the TLM level a fixed SystemC based sub-system with user logic which is eventually to be mapped into the programmable FPGA fabric. We will quantify the value of extending a platform like Zynq at the transaction-level by comparing design flows with and without usage of TLM models.
A Generic Language for Hardware & Software, Are We There Yet? An Explorative Case Study Examining the Usage of SystemC for Multicore Programming
The recent migration from uniprocessor systems to multicore hardware-architectures has coerced the invention of effective tools that alleviate the process of developing concurrent software. Whereas the software industry has channelized its efforts into the development of open-source standardizations such as OpenMP, the increasing adoption of system-level design methodologies has provided designers with a multitude of tools, SystemC being one such which enables hardware-software codesign and permits the modeling of concurrency.
In this paper, we examine both approaches through a comparative study of the process of developing concurrent software using OpenMP and SystemC. Specifically, we choose to implement the Quicksort algorithm, as it is easily parallelizable and hence illustrates properties that resemble that of typical concurrent software. We first showcase the process of modeling a concurrent version of Quicksort, and then discuss its implementations using OpenMP and SystemC. We then compare the performance (execution-time and execution-speedup) and ease of implementation of the variants, including a sequential implementation of Quicksort. Experimental results suggest that although it permits the development of concurrent software, due to performance issues, SystemC does not seem to be a suitable platform for multicore programming.
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