DVCon 2012 Verification Paper Archive – UVM, Low Power, Mixed Signal and More!
By Richard Goering on May 1, 2012Comments(0)Filed under: Industry Insights, DVCon, low power, TLM, SoC, Accellera, verification, IP, Mixed-Signal, mixed signal, Functional Verification, UVM, SystemVerilog, assertions, SVA, coverage, UVM-MS, debugging, PSL, virtual prototypes, DVCon 2012,covergroups, DVCon presentations, DVCon papers
In late April, a wealth of information on IC functional verification became available at the DVCon web site. Both papers and slides are now available for dozens of high-quality presentations given at the DVCon 2012 conference, which was held Feb. 27-March 1, 2012 in Santa Clara, California. You can view the list of sessions here.
Cadence contributed heavily to DVCon this year, and what follows is a listing of Cadence-authored or co-authored papers now available for viewing and downloading. Happy reading!
Session 1: Low Power Techniques
Paper: The Case for Low-Power Simulation-to-Implementation Equivalence Checking
Presented by: Himanshu Bhatt, Cadence
Summary: I attended this paper, and found it to be a good summary that shows how equivalence checking fits into the low-power verification flow. While power formats unify intent, the paper notes, implementation and verification tools may interpret the information differently. Equivalence checking can formally prove that simulation matches the original power intent and RTL.
Session 1P: Poster Session 1
Paper: PSL/SVA Assertions in SPICE
Presented by: Donald O'Riordan, Cadence
Summary: This paper shows how Property Specification Language (PSL) and SystemVerilog Assertions (SVA) assertion semantics can be extended to, and evaluated within, a SPICE-based simulator. It presents multiple examples and simulation results.
Paper: New Challenges in Verification of Mixed-Signal IP and SoC Design
Presented by: Qi Wang, Cadence
Summary: Mixed-signal blocks with advanced power management techniques can pass simulation but fail in silicon. This paper proposes that a static verification methodology can help catch electrical failures.
Session 2: UVM Techniques
Paper: Register This! Experiences Applying UVM Registers
Presented by: Kathleen Meade, Cadence
Summary: Controlling and monitoring registers and memories comprises a large part of typical functional verification projects. This paper shows how the Accellera UVM-REG register and memory package can help, and provides some practical guidelines for register management gleaned from real project experience.
Session 2P: Poster Session 2
Paper: UVM Do's and Don'ts for Effective Verification
Presented by: Kathleen Meade, Cadence
Summary: This presentation provides tips and best practices using specific pointers and code examples, gathered from live projects worldwide. Topics include configuration, the objection mechanism, the register package, and transaction level modeling (TLM).
Session 4: Verification Benchmarking and Efficiency
Paper: Yikes! Why is My SystemVerilog Testbench so Slow?
Presented by: Justin Sprague, Cadence
Summary: While SystemVerilog added many useful new features, many verification engineers have experienced slower simulation. This paper shows why - and tells what you can do about it.
Session 6: Mixed-Signal Verification
Paper: From Spec to Verification Closure: A Case Study of Applying UVM-MS for First Pass Success to a Complex Mixed-Signal SoC Design
Presented by: Neyaz Khan, Maxim
Summary: This paper shows why metric-driven verification and UVM are needed for mixed-signal verification, and presents an example based on a noise cancelling receiver block within a mixed-signal SoC. I attended and wrote a blog post about this paper.
Session 7: Verification and Debugging Tips
Paper: Memory Debugging of Virtual Prototypes with TLM 2.0
Presented by: George Frazier, Cadence
Summary: Memories are commonly modeled as TLM 2.0 components in SystemC-based virtual prototypes. This paper shows how TLM 2.0 memory debugging can be used to investigate problems familiar to virtual prototype designers.
Session 8: Getting to Coverage Closure
Paper: Bringing Continuous Domain into SystemVerilog Covergroups
Presented by: Prabal Bhattacharya, Cadence
Summary: This paper proposes a set of requirements for specifying functional coverage in an analog or mixed-signal block. It explains how the real number data type can be introduced into a SystemVerilog coverpoint specification, enabling a complete coverage specification for a mixed-signal verification environment.
Note: An audio archive of the DVCon 2012 panel, "The Resurgence of Chip Design," is available here. You can listen to individual sections of the panel or download the full MP3 file. My blog summary of the panel is locatedhere.
Richard Goering
In late April, a wealth of information on IC functional verification became available at the DVCon web site. Both papers and slides are now available for dozens of high-quality presentations given at the DVCon 2012 conference, which was held Feb. 27-March 1, 2012 in Santa Clara, California. You can view the list of sessions here.Cadence contributed heavily to DVCon this year, and what follows is a listing of Cadence-authored or co-authored papers now available for viewing and downloading. Happy reading!
Session 1: Low Power Techniques
Paper: The Case for Low-Power Simulation-to-Implementation Equivalence Checking
Presented by: Himanshu Bhatt, Cadence
Summary: I attended this paper, and found it to be a good summary that shows how equivalence checking fits into the low-power verification flow. While power formats unify intent, the paper notes, implementation and verification tools may interpret the information differently. Equivalence checking can formally prove that simulation matches the original power intent and RTL.
Session 1P: Poster Session 1
Paper: PSL/SVA Assertions in SPICE
Presented by: Donald O'Riordan, Cadence
Summary: This paper shows how Property Specification Language (PSL) and SystemVerilog Assertions (SVA) assertion semantics can be extended to, and evaluated within, a SPICE-based simulator. It presents multiple examples and simulation results.
Paper: New Challenges in Verification of Mixed-Signal IP and SoC Design
Presented by: Qi Wang, Cadence
Summary: Mixed-signal blocks with advanced power management techniques can pass simulation but fail in silicon. This paper proposes that a static verification methodology can help catch electrical failures.
Session 2: UVM Techniques
Paper: Register This! Experiences Applying UVM Registers
Presented by: Kathleen Meade, Cadence
Summary: Controlling and monitoring registers and memories comprises a large part of typical functional verification projects. This paper shows how the Accellera UVM-REG register and memory package can help, and provides some practical guidelines for register management gleaned from real project experience.
Session 2P: Poster Session 2
Paper: UVM Do's and Don'ts for Effective Verification
Presented by: Kathleen Meade, Cadence
Summary: This presentation provides tips and best practices using specific pointers and code examples, gathered from live projects worldwide. Topics include configuration, the objection mechanism, the register package, and transaction level modeling (TLM).
Session 4: Verification Benchmarking and Efficiency
Paper: Yikes! Why is My SystemVerilog Testbench so Slow?
Presented by: Justin Sprague, Cadence
Summary: While SystemVerilog added many useful new features, many verification engineers have experienced slower simulation. This paper shows why - and tells what you can do about it.
Session 6: Mixed-Signal Verification
Paper: From Spec to Verification Closure: A Case Study of Applying UVM-MS for First Pass Success to a Complex Mixed-Signal SoC Design
Presented by: Neyaz Khan, Maxim
Summary: This paper shows why metric-driven verification and UVM are needed for mixed-signal verification, and presents an example based on a noise cancelling receiver block within a mixed-signal SoC. I attended and wrote a blog post about this paper.
Session 7: Verification and Debugging Tips
Paper: Memory Debugging of Virtual Prototypes with TLM 2.0
Presented by: George Frazier, Cadence
Summary: Memories are commonly modeled as TLM 2.0 components in SystemC-based virtual prototypes. This paper shows how TLM 2.0 memory debugging can be used to investigate problems familiar to virtual prototype designers.
Session 8: Getting to Coverage Closure
Paper: Bringing Continuous Domain into SystemVerilog Covergroups
Presented by: Prabal Bhattacharya, Cadence
Summary: This paper proposes a set of requirements for specifying functional coverage in an analog or mixed-signal block. It explains how the real number data type can be introduced into a SystemVerilog coverpoint specification, enabling a complete coverage specification for a mixed-signal verification environment.
Note: An audio archive of the DVCon 2012 panel, "The Resurgence of Chip Design," is available here. You can listen to individual sections of the panel or download the full MP3 file. My blog summary of the panel is locatedhere.
Richard Goering
'via Blog this'
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