Functional Verification: Cadence Technical Webinars

Some amount of marketing is inevitable, but I bet there will still be some good stuff here...  :-)

From: Cadence Design Systems <corpmark2@cadence.com>
Date: Wed, Jul 25, 2012 at 5:46 PM
Subject: Advance Your Functional Verification Skills with Cadence Technical Webinars

Advance Your Functional Verification Skills with Cadence Technical Webinars Join Cadence® verification experts for a series of technical webinars on the most relevant topics in functional verification. We'll introduce you to the latest techniques, best practices, methodologies, and support services you need for developing and verifying your silicon designs—productively and profitably! In these concise 1-hour sessions, we'll address hot topics including: SystemVerilog-based debug Better verification performance Power shutoff (PSO) verification Best practices for UVM sequences Implementing multi-language UVM Formal apps to automate verification Combining a metric-driven verification (MDV) flow with an ISO26262 flow TLM 2.0 communication mechanisms and how they are replicated in e Assertion-based verification (ABV) techniques for your ARM®ACE™ implementation You'll get the answers you need to adopt new approaches. You can also follow up with our technical experts, who will set you up with our Incisive® Verification Kit to hone your skills. These webinars are designed to be methodology- and application-based, not a marketing pitch. Plus, you don't need to travel—you can view these presentations and demonstrations from the comfort of your home or office! For more information, or to register: https://www.secure-register.net/cadence/fv_webinars_2h_2012 Application-Specific Webinars (all times below are 9:00 am PT) August 8: Formal Apps to Automate Mainstream Verification Challenges This webinar will show how technology and methodology can be packaged into "apps" that focus on high-value problems that are more efficiently solved using formal-based methods, and can be automated such that very little knowledge of formal or assertion-based verification (ABV) is required… August 21: Why Debug at the Signal Level When SystemVerilog Class-Based Debug is So Simple? This webinar will walk users through the advantages of using the debug power of SimVision within a complex class-based SystemVerilog environment for both interactive and post-process debug... September 11: No More Wrappers – New Interface Between e and SystemC TLM 2.0 Transaction-level models (TLMs) can be used in a number of ways to speed up the design and verification effort for SoCs and their software layers. The last several years has seen strong adoption of SystemC TLM 2.0 for high-level modeling; it has become the de-facto standard for such models… September 18: Is SystemVerilog the Future of Analog Modeling? A significant speed-up in simulation performance can be achieved by replacing the analog portions of a design with functionally equivalent real-number models using real/wreal functionality in Verilog-AMS and/or SystemVerilog to achieve a 100–500x performance boost for top-level SoC verification… September 25: Combining the Best of Both in an MDV Flow – Simulation and Formal There exist many benefits to simulation technology within a metric-driven verification (MDV) flow, and an equal number of benefits using formal technology. Now users can combine these metrics together to take advantage of the best in each… October 16: 5 Steps to Your First Power Shutoff (PSO) Verification Making the leap to your first PSO circuit can be daunting. Do the isolation cells properly insulate the shutoff domain? Do the retention registers enable the SoC to return to full-power properly? Have enough tests been run to cover the power control module?...  October 25: UVM SystemVerilog in a Multi-Language SoC World: UVM-ML While the Accellera Systems Initiative UVM standard is defined for SystemVerilog, its architecture can support multi-language verification environments. Every SoC has some mix of models coded to IEEE and ANSI language standards… November 6: Integrating Chip Verification into an ISO26262 Traceability Flow This webinar will show how to combine a metric-driven verification flow typically used in functional verification with an ISO26262 requirements management flow. The solution entails electronically transferring requirements into the verification flow… November 13: UVM Sequences:  Best Practices for Efficiency and Reuse One of the primary goals of the UVM is to reduce the cost and burden of writing tests. This is accomplished by providing an abstract test definition interface in the form of sequences. Subsequently, much of the complexity involved with driving and monitoring the DUT is absorbed in UVM verification components (UVCs). November 27: SimVision Simplifies UVM SystemVerilog Macro Debug This webinar will introduce the user to the latest in macro debug capabilities offered within the SimVision debug solution. Users of UVM-based environments, where macros are heavily utilized, will find this webinar particularly useful…  December 4: Better Verification Performance – The Ideal Holiday Gift We fight the performance battle all year and growing designs, tests, and test suites constantly make it more difficult. Luckily, Cadence is also constantly developing new capabilities to improve verification performance…  December 11: ACE Assertion-Based Dynamic, Formal, and Metric-Driven Verification Techniques with "ABVIP" To achieve first-pass success, the sophistication of ARM ACE-based designs must be matched by a comprehensive verification approach. This webinar will show how formal and assertion-based verification techniques, combined with assertion-based verification IP (ABVIP), can be used in concert with popular UVM testbench VIP… For more information, or to register: https://www.secure-register.net/cadence/fv_webinars_2h_2012

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