Seminar 8/26 11:30AM FtC - New Wave of Architectures for Media-Rich Workloads by Sam Naffziger (AMD Fort Collins)

---------- Forwarded message ----------
From: Loke, Alvin <Alvin.Loke@amd.com>
Date: Wed, Aug 24, 2011 at 7:42 AM
Subject: IEEE SSCS Seminar - Technology Impacts from the New Wave of Architectures for Media-Rich Workloads by Sam Naffziger (AMD Fort Collins)

When: Friday, August 26, 2011 11:30 AM-12:45 PM (UTC-07:00) Mountain Time (US & Canada).

Where: AMD Fort Collins Campus (NW corner of Ziegler and Harmony Roads)

 

Note: The GMT offset above does not reflect daylight saving time adjustments.

 

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SEMINAR TIME HAS BEEN MOVED TO START AT 11:30AM DUE TO LATE SEMINAR ROOM CONFLICT

 

RSVP            http://gomartin.net/sscs/2011/rsvp_2011_08_26.htm

 

DETAILS http://ewh.ieee.org/r5/denver/sscs/2011_08_Naffziger.html

 

TITLE           Technology Impacts from the New Wave of Architectures for Media-Rich Workloads

 

ABSTRACT

This presentation is an encore of an invited plenary talk recently delivered at the 2011 Symposia on VLSI Technology and Circuits in Kyoto, Japan.

As the growth in rich and multi-media workloads begin to dominate the compute cycles of our next-generation processors, a revolution in architecture is taking place to efficiently deal with them.  This revolution involves the synergistic combination of parallel and serial computation elements on-die. This co-location makes for a rapidly evolving set of technology challenges. With power limits front and center, the need for efficient, dense logic with high-bandwidth interconnect makes the computing industry more dependent than ever on continuing VLSI technology improvements. This talk will explore these trends and the implications for next-generation process development.

 

BIOGRAPHY OF SPEAKER

Sam Naffziger received the BSEE degree from the California Institute of Technology, Pasadena, CA, in 1988, and the MSEE degree from Stanford University, Stanford, CA, in 1993.  He has over 22 years experience in microprocessor design, having led the implementation of PA-RISC, Itanium and AMD processors working for Hewlett Packard, Intel and AMD.  He joined AMD in 2006, helping start the Mile High Design Center in Fort Collins, CO where he has been responsible for power and frequency optimization of mainstream processors and is the power efficiency architect for AMD's products.  He holds 96 U.S. patents on processor circuits and architecture and has over 25 IEEE publications and presentations.  Mr. Naffziger chaired the Digital subcommittee of the International Solid-State Circuits Conference for 5 years, was Associate Editor for the JSSC, and is a Corporate Fellow at AMD.