Cool conference if you are interested in hardware design verification, or even design itself.
Cheers,
Connie
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February 27 - March 1, 2012 DVCon is the premier conference for functional design and verification, focused on bringing information from the leading edge of technology, techniques, standards and methods. |
2012 Call for Abstracts & Tutorials & Panels
DVCon Expo
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Tuesday, February 28, 3:30 - 6:30 pm
Wednesday, February 29, 4:30 - 7:00 pm | |
DVCon in San Jose
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Top 10 Reasons to attend and exhibit at DVCon
| - Network face to face with people
- Give your customers an opportunity to meet the experts!
- You will meet your peers, mentors, leaders and acquaintances for support and friendship!
- Learn new industry trends
- Open doors for future sales calls
- Imagine and learn about the future
- Invest in your success!
- Wonderful educational opportunities
- Generate excitement for new products/services
- The People!
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DVCon is the premier conference on the application of languages, tools and methodologies for the design and verification of electronic systems and integrated circuits. The focus of the conference is on the usage of specialized design and verification languages such as Verilog, SystemVerilog, VHDL, PSL SystemC, e, and VERA, as well as general purpose languages such as C and C++. Tools and methodologies include the use of testbench automation, hardware-assisted verification, hardware/software co-verification, assertion-based and formal verification, and transaction-level system design and verification.
Conference Schdule: Monday:
February 27
| Tuesday
February 28- Technical Session
- Panel Discussion
- Exhibiton
| Wednesday
February 29
- Keynote Speaker
- Technical Session
- Panel Discussion
- Exhibition
| Thursday
March 1
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| Accellera, the sponsor of DVCon, celebrates its 11 years of Electronic Design Automation (EDA) and Intellectual Property (IP) standards development at DVCon. |
| © Copyright 2012 DVCon |
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