Date: Fri, May 4, 2012 at 9:22 AM
Subject: IEEE SSCS Seminar - Resonant Clock Design for a Power-efficient High-volume x86–64 Microprocessor by Visvesh Sathe & Sam
Subject: IEEE SSCS Seminar - Resonant Clock Design for a Power-efficient High-volume x86–64 Microprocessor by Visvesh Sathe & Sam
When: Friday, May 18, 2012 10:00 AM-11:00 AM (UTC-07:00) Mountain Time (US & Canada).
Where: AMD Fort Collins (NE corner of Harmony and Ziegler, 3rd floor)
Note: The GMT offset above does not reflect daylight saving time adjustments.
*~*~*~*~*~*~*~*~*~*
TITLE Resonant Clock Design for a Power-efficient High-volume x86–64 Microprocessor
ABSTRACT
This presentation is an extended encore of a paper recently delivered at the 2012 International Solid-State Circuits Conference (ISSCC) in San Francisco, CA.
AMD's 4+ GHz x86–64 core codenamed "Piledriver" employs resonant clocking to reduce clock distribution power up to 24% while maintaining a low clock-skew target. To support testability and robust operation at the wide range of operating frequencies required of a commercial processor, the clock system operates in two modes: direct-drive and resonant. Leveraging favorable factors such as the availability of two thick top-level metals, high operating frequency, clock-load density, and the existing clock-design methodology, the resonant-clock mode was designed to enable both reduced average power dissipation, and improved peak-power-constrained performance, with minimal area impact. This work represents a volume production-enabled implementation of resonant clock technology, and is plan of record for mid-2012 product offerings.
BIOGRAPHY OF SPEAKERS
Visvesh Sathe (S'02-M'07) received the B.Tech. degree in electrical engineering in 2001 from the Indian Institute of Technology, Bombay, India, and the M.S. and Ph.D. degrees in electrical engineering and computer science in 2004 and 2007 respectively from the University of Michigan, Ann Arbor. While at Michigan, his research focused on low-energy circuit design with particular emphasis on resonant-clocked digital design. He has held internship positions at the IBM T.J Watson Research Center and Cyclos Semiconductor, a start-up focusing on resonant-clocked microprocessors. In 2007, he joined the power management group at Advanced Micro Devices, Fort Collins, CO, where he is now Member of Technical Staff exploring and implementing power reduction techniques for next-generation processors. Dr. Sathe has authored 13 technical publications and two US patents.
Sam Naffziger received the BSEE degree from the California Institute of Technology, Pasadena, CA, in 1988, and the MSEE degree from Stanford University, Stanford, CA, in 1993. He has over 22 years experience in microprocessor design, having led the implementation of PA-RISC, Itanium and AMD processors working for Hewlett Packard, Intel and AMD. He joined AMD in 2006, helping start the Mile High Design Center in Fort Collins, CO where he has been responsible for power and frequency optimization of mainstream processors and is the power efficiency architect for AMD's products. He holds 96 U.S. patents on processor circuits and architecture and has over 25 IEEE publications and presentations. Mr. Naffziger chaired the Digital subcommittee of the International Solid-State Circuits Conference for 5 years, was Associate Editor for the JSSC, and is a Corporate Fellow at AMD.
No comments:
Post a Comment