Cheers,
Connie
---------- Forwarded message ----------
From: <Deepti_Mishra@artechinfo.com>
Date: Mon, May 3, 2010 at 10:09 AM
Subject: Need Verification Engineer in COLORADO SRPINGS, CO
To: c.odell@co-consulting.net
Job Title: Verification Engineer
Location: COLORADO SRPINGS, CO
Duration: 3-6 Months
Job Description:
Please note this is a high priority req for a special project. Contract length is for 3 months and the manager is looking to start someone as soon as possible. The manager has specified specifics he is looking for below:
Experience with highly randomized TestBenches and SystemVerilog is required. OVM experience preferred. Must have experience with assertions, functional coverage points, and code coverage. Questa simulator experience is preferred. Experience with SAS/SATA protocols is a plus.
DUTIES >>
The engineer will be a member of a SAS Expander verification team. Typical activities would include understanding scope of system verification and verifying IP as per specifications. The engineer is responsible for ensuring the IP is functionally correct through the creation of test plans and test cases using an OVM based verification environment. Participation in peer verification reviews will also be involved.
SKILLS >>
Experience with highly randomized TestBenches and SystemVerilog is required. OVM experience preferred. Must have experience with assertions, functional coverage points, and code coverage. Questa simulator experience is preferred. Experience with SAS/SATA protocols is a plus.
Experience in verification/validation. This candidate would have been through the IC development flow from start to finish on more than one project. Typical background would include SOC testbench development using advance verification techniques such as VMM or OVM, development of test plans and test suites, regression execution and analysis and compliance testing. Proficiency in a high level programming/verification knowledge such as; OVM, VMM, C/C++, Verilog, System verilog and assembly level language. Experience with storage serial protocols is a plus, e.g. ethernet, PCI-Express, SAS etc.
EDUCATION >>
Bachelors required. Masters a plus
From: <Deepti_Mishra@artechinfo.com>
Date: Mon, May 3, 2010 at 10:09 AM
Subject: Need Verification Engineer in COLORADO SRPINGS, CO
To: c.odell@co-consulting.net
Job Title: Verification Engineer
Location: COLORADO SRPINGS, CO
Duration: 3-6 Months
Job Description:
Please note this is a high priority req for a special project. Contract length is for 3 months and the manager is looking to start someone as soon as possible. The manager has specified specifics he is looking for below:
Experience with highly randomized TestBenches and SystemVerilog is required. OVM experience preferred. Must have experience with assertions, functional coverage points, and code coverage. Questa simulator experience is preferred. Experience with SAS/SATA protocols is a plus.
DUTIES >>
The engineer will be a member of a SAS Expander verification team. Typical activities would include understanding scope of system verification and verifying IP as per specifications. The engineer is responsible for ensuring the IP is functionally correct through the creation of test plans and test cases using an OVM based verification environment. Participation in peer verification reviews will also be involved.
SKILLS >>
Experience with highly randomized TestBenches and SystemVerilog is required. OVM experience preferred. Must have experience with assertions, functional coverage points, and code coverage. Questa simulator experience is preferred. Experience with SAS/SATA protocols is a plus.
Experience in verification/validation. This candidate would have been through the IC development flow from start to finish on more than one project. Typical background would include SOC testbench development using advance verification techniques such as VMM or OVM, development of test plans and test suites, regression execution and analysis and compliance testing. Proficiency in a high level programming/verification knowledge such as; OVM, VMM, C/C++, Verilog, System verilog and assembly level language. Experience with storage serial protocols is a plus, e.g. ethernet, PCI-Express, SAS etc.
EDUCATION >>
Bachelors required. Masters a plus
| Deepti Mishra Executive Staffing | |
240 Cedar Knolls Road, Suite 100 | Cedar Knolls, NJ 07927 | |
| Office: 973.993.9383 Ext. 3397 | Fax: 973.993.9366 | |
| Email: Deepti_Mishra@artechinfo.com | Website: www.artechinfo.com | |
Artech is the NMSDC National Supplier of the Year! | |
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