I have heard of multiple reqs for SystemC modeling work on a DSP-based chip, which is being quietly staffed as follows:
"We want to engage a small team to model the system primarily as an aid to FW development. We intend the model to have an IDE with the same look and feel as the final IDE. Would modeling be up your alley or are you more tied into verification? Since this is a modeling project rather than verification it is legitimate to reverse engineer our Verilog RTL as part of building the model"
Cheers,
Connie L. O'Dell
Sr. Verification Specialist
c.odell@co-consulting.net
303-641-5191
_____________________________________________
CO Consulting - Boulder, CO - http://co-consulting.net
If you are interested in this position (kinda busy getting a new design out myself), and since we are not hiring more SystemC people right now ourselves, I have agreed to collect people's responses and forward to hiring manager. I have no affiliation with them, just like to see people matched up with gigs sooner rather than later. :-) I can tell you that the work is not located here, or in CA, if it matters. They do want an onsite training period in a midwestern location, at the contract start, but otherwise remote work from elsewhere in the US is OK. Feel free to forward this if you know of someone who may be qualified and interested.
Cheers,
Connie L. O'Dell
Sr. Verification Specialist
c.odell@co-consulting.net
303-641-5191
_____________________________________________
CO Consulting - Boulder, CO - http://co-consulting.net
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