In this webinar we give a short introduction to UVM, the Universal Verification Methodology for SystemVerilog, by taking advantage of Easier UVM, a set of coding guidelines and a code generator that creates UVM code compliant to those guidelines. Easier UVM is an effective way of learning and adopting UVM, and furthermore the Easier UVM guidelines and code generator are freely available for use. Easier UVM was created to help individuals and project teams learn and then become productive with UVM as quickly as possible. | Full description: Easier UVM - Making Verification Methodology more Productive
Schedule and Registration: Friday October 17th: For Europe and Asia Time: 10am-11am (BST - UK) 11am-12pm (CEST) 2.30pm-3.30pm (IST) Friday October 17th: For North America (also Europe if late afternoon preferred) Time: 10am-11am (PDT) 11am-12pm (CDT) 1pm-2pm (EDT) 6pm-7pm (BST - UK) Want to find out more about Doulos first? Check out: www.doulos.com.
| Ready for full scope training? Check out the leading training programs from Doulos Full Doulos training schedule Upcoming Webinar in October |
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