DVClub UPDATE - Newsletter Spring 2012

From: DVClub <admin@dvclub.org>
Date: Thu, Apr 12, 2012 at 12:15 PM
Subject: DVClub UPDATE - Newsletter Spring 2012

Is this email not displaying correctly? View it in your browser. In this Issue:       Silicon Valley - April 13th       Bristol/Cambridge/Grenoble - April 23rd       Give Us Your Opinion       Sponsored Content Silicon Valley - Tomorrow - April 13th The Cortex-A15 Verification Story Bill Greene, Austin CPU Validation Manager, ARM Micah McDaniel, Senior Principal Design Engineer, ARM Abstract: Learn the details of verifying the Cortex-A15 MPCore: this processor has an out-of-order superscalar pipeline with a tightly-coupled low-latency level-2 cache which can be up to 4MB in size. It can be configured in clusters with up to 4 cores, and supports MP cache coherency in hardware.  Additional improvements in floating point and NEON™ media performance result in devices that deliver the next-generation user experience for consumers as well as high-performance computation for web infrastructure applications. This processor introduces new technology that enables efficient handling of complex software environments including full hardware virtualization, Large Physical Address Extensions (LPAE) addressing up to 1TB of memory as well as error correction capability for fault-tolerance and soft-fault recovery. SOLD OUT! Slides will be posted on the website on Monday, April 16th.   Bristol/Cambridge/Grenoble - April 23rd Easier UVM John Aynsley, CTO, Doulos Abstract: UVM is the current hot topic in verification and this DVClub will focus on adopting UVM with examples presented illustrating a set of guidelines on the use of the UVM class library for functional verification. TVS will present a quick talk on developing and delivering UVM compliant VIP. User papers will also be featured. Attend at at a venue convenient to you - choose from Bristol, Cambridge or Grenoble. Additional venues may be offered as well. You will also be able to access the talk remotely, if you are unable to attend physically. Register Give Us Your Opinion What Do You Want? We want to hear from YOU - our Design Verification Engineers. How can DVClub best serve YOUR needs for networking, community, learning, education, and career development? Let us know how much you agree with the following statements: I attend DVClub primarily for learning and skill development. lowest 1   2   3   4   5   6   7   8   9   10   highest I attend DVClub primarily for career development. lowest 1   2   3   4   5   6   7   8   9   10   highest I want more topics on SoC Verification. lowest 1   2   3   4   5   6   7   8   9   10   highest I want more topics on Functional Verification. lowest 1   2   3   4   5   6   7   8   9   10   highest I want more topics on Testplan Development / Documentation. lowest 1   2   3   4   5   6   7   8   9   10   highest I want more topics on Standardization. lowest 1   2   3   4   5   6   7   8   9   10   highest Sponsored Content Gathering Clouds - 11 New interfaces that will shape cloud infrastructure - by Tom Hackett, Cadence Design Systems Everyone is talking about "The Cloud", but what does it mean for hardware developers and how will it impact verification engineers?  Find out in this article on ChipEstimate.com and learn about the 11 new interfaces that will shape cloud infrastructure: http://bit.ly/GCybHN.  Incisive Performance Scales to Meet Advanced Node SoC Verification Requirements Its' all about RTL simulation.  I mean gates.  I mean turn-around-time.  Project-level productivity.  Mixed-signal.  Low-power. UVM.  And. And. And. … And the reality is that advanced node SoCs are so complex that it is truly about all of these.  Our new white paper details a systematic approach to verification performance you can use immediately at all levels from core simulation to advanced technologies and methodologies.     Recent Blogs Memory BISTing Your SoC Memory Built-In Self-Test (BIST) has existed for as long as there have been modern SoCs. With today's advanced SoCs containing literally hundreds and even thousands of SRAM memories, clustered in many memory subsystems throughout the SoC, both memory BIST as well as Built-In-Self-Repair (BISR) technology are increasingly important to insure the highest possible yield. As SoC's become increasingly more complex and issues arrise in meeting power, performance, and other targets, additional solutions must be found. ARM teamed up with Mentor to provide customers a comprehensive and automated solution to address these issues. Read More >> Using Cache Coherency to Verify the AMBA4 Protocol Paul Martin from ARM presented at the Jasper User Group Meeting on formal verification - specifically how modern multi-core processors now require much more sophisticated cache control than before, ensuring that all devices in the system have the same view of shared data, known as cache coherency. ARM in particular has created some quite sophisticated protocols, AXI Coherency Extensions (ACE), under the AMBA 4 umbrella. Read More >> DVClub welcomes our newest GOLD Sponsor: Breker Verification Systems solves the challenge of functional verification for complex system-on-a-chip (SoC) designs. Our Trek™ model-based test generation tool is proven in production at leading semiconductor companies. It enables design managers and verification engineers to realize measurable productivity gains, speed coverage closure and easily reuse verification knowledge. follow on Twitter  | forward to a friend  If you need assistance, please contact us at  admin@dvclub.org Design Verification Club 1250 S. Capitol of Texas Hwy Building 1, Suite 520 Austin, TX 78746 Copyright © 2012 Design Verification Club, All rights reserved.

Design Verification Club · 1250 S. Capitol of Texas Hwy · Building 1, Suite 520 · Austin, TX 78746